公开(公告)号：US10430117B2

公开(公告)日：2019-10-01

申请号：US15790794

申请日：2017-10-23

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

公开(公告)号：US10318301B2

公开(公告)日：2019-06-11

申请号：US15692225

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F9/30 ,  G11C16/04

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

公开(公告)号：US20190121576A1

公开(公告)日：2019-04-25

申请号：US15790794

申请日：2017-10-23

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0659 ,  G06F3/0616 ,  G06F3/0622 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/10 ,  G06F2212/1008 ,  G06F2212/2022

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A read request is received at a controller of a NAND device. Here, the read request includes a logical address and a physical address. A a verification component that corresponds to the physical address is retrieved a NAND array of the NAND device. A verification of the read request is computed using the logical address, the physical address, and the verification component. A read operation is then modified based on the verification.

公开(公告)号：US20190065204A1

公开(公告)日：2019-02-28

申请号：US15692225

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F9/30

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.

公开(公告)号：US20190065088A1

公开(公告)日：2019-02-28

申请号：US15690933

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06

Abstract: Devices and techniques for random access memory power savings are disclosed herein. Data contained in RAM is compressed in response to obtaining a trigger. Here, the RAM organized into several discrete hardware components with a corresponding power control. The data contained in the RAM is replaced with the compressed data to free a discrete hardware component of the RAM. The discrete hardware component is then powered down via the corresponding power control.

公开(公告)号：US11922060B2

公开(公告)日：2024-03-05

申请号：US17373239

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G06F13/16 ,  G11C16/04 ,  H03M7/30

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2212/401 ,  G11C16/0483 ,  H03M7/30

Abstract: Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.

公开(公告)号：US11735269B2

公开(公告)日：2023-08-22

申请号：US17589172

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Reddy Singidi ,  Jianmin Huang ,  Preston Allen Thomson ,  Sebastien Andre Jean

IPC: G11C8/00 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3445 ,  G11C11/5671 ,  G11C16/3409 ,  H10B41/27 ,  H10B43/27

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.

公开(公告)号：US11635899B2

公开(公告)日：2023-04-25

申请号：US17573224

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US11409651B2

公开(公告)日：2022-08-09

申请号：US17051995

申请日：2019-05-15

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Greg A. Blodgett

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/14

Abstract: Devices and techniques for host accelerated operations in managed NAND devices are described herein. A host logical-to-physical (L2P) table of the NAND device has an associated map. Entries in the map correspond to one or more logical addresses (LA) and indicate whether the host L2P table is current for those LAs. If the table is not current, then a request will bypass the host L2P table, using a standard device L2P lookup instead. Otherwise, the host L2P table can be used.

公开(公告)号：US11309040B2

公开(公告)日：2022-04-19

申请号：US17147222

申请日：2021-01-12

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F1/32 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F12/14 ,  G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08 ,  G06F1/3234 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.