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公开(公告)号：US20200005855A1
公开(公告)日：2020-01-02
申请号：US16557933
申请日：2019-08-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yasuo Satoh , Tyler J. Gomm
IPC: G11C11/4076 , H03K3/017 , H03K23/00 , H03M7/16 , G11C29/02
Abstract: Apparatuses and methods for maintaining a duty cycle error counter. An example apparatus may a duty cycle detect circuit configured to receive a clock signal and to detect a duty cycle error of the clock signal. The duty cycle detect error includes a counter configured to store a count value indicating the duty cycle error using Gray code. The counter is adjusted in response to detection of non-zero duty cycle error, and the counter is configured to convert the count value from Gray code to binary code as a binary count value. The duty cycle detect circuit is further configured to provide a duty cycle error signal based on the binary count value. The example apparatus further comprising a duty cycle correction circuit configured to adjust a duty cycle of the clock signal based on the duty cycle error signal.
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公开(公告)号：US10373671B1
公开(公告)日：2019-08-06
申请号：US15948422
申请日：2018-04-09
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm
Abstract: A device may include an integrated circuit and a jitter generator located on the integrated circuit. The jitter generator may include a random number generator to generate a random number in response to a clock input signal. The jitter generator may also include delay-causing circuitry to receive the clock input signals, where the delay-causing circuitry may create a delayed clock input signal. The jitter generator may also include a phase mixer to receive the random number, the delayed clock input signal, and the clock input signal, where the phase mixer additionally outputs a clock output signal having the clock input signal and having jitter.
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公开(公告)号：US20170310325A1
公开(公告)日：2017-10-26
申请号：US15644401
申请日：2017-07-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm
IPC: H03K21/38
CPC classification number: H03K21/38
Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.
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公开(公告)号：US12068751B2
公开(公告)日：2024-08-20
申请号：US17852657
申请日：2022-06-29
Applicant: Micron Technology, Inc.
Inventor： Eric J. Stave , Tyler J. Gomm
IPC: G11C11/4076 , G11C7/22 , H03K5/1534 , H03K5/156 , H03K19/21
CPC classification number: H03K5/1565 , G11C7/222 , H03K5/1534 , H03K19/21
Abstract: A device includes a clock input circuit that when in operation receives a clock signal and transmits an internal clock signal based on the clock signal. The device also includes an internal clock generator coupled to the clock input circuit to receive the internal clock signal, wherein the internal clock generator comprises clock adjustment circuitry that when in operation generates a phase controlled internal clock signal having subsequent clock edges based upon a single clock edge of the internal clock signal, wherein the phase controlled internal clock signal comprises a first frequency as a multiple of a second frequency of the internal clock signal.
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公开(公告)号：US11115007B2
公开(公告)日：2021-09-07
申请号：US16294640
申请日：2019-03-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K3/037 , H03K3/017 , H03K19/20 , G11C11/4074 , G11C11/408 , G11C11/4076 , G11C7/10 , G11C11/4093 , G11C7/22
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
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Patent Agency Ranking
公开(公告)号：US10270431B2
公开(公告)日：2019-04-23
申请号：US15717610
申请日：2017-09-27
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm , Yasuo Satoh
IPC: H03K19/20 , H03K3/037 , G11C11/4074 , G11C11/408
Abstract: Methods and apparatuses of a two-phase flip-flop with symmetrical rise and fall times are disclosed herein. An example apparatus may include a clock generator circuit including a two-phase flip-flop circuit configured to provide an output signal. The two-phase flip-flop circuit includes a two-phase flip-flop and a driver circuit. The two-phase flip-flop is configured to provide a first driver control signal and a second driver control signal responsive to a clock signal. The first driver control signal and the second driver control signal are complementary. The driver circuit is configured to provide the output signal responsive to the first driver control signal and the second driver control signal.
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公开(公告)号：US10164642B2
公开(公告)日：2018-12-25
申请号：US15644401
申请日：2017-07-07
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tyler J. Gomm
Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.
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18.发明授权Apparatuses and methods for controlling delay circuits during an idle state to reduce degradation of an electrical characteristic 有权用于在空闲状态期间控制延迟电路以减少电特性劣化的装置和方法公开(公告)号：US09479151B2
公开(公告)日：2016-10-25
申请号：US14046786
申请日：2013-10-04
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm , Scott D. Van De Graaff
CPC classification number: H03K5/14 , H03K2005/00215
Abstract: Delay circuits may be controlled by apparatuses and methods during an idle state to reduce degradation of an electrical characteristic. An example apparatus includes a delay line circuit including a plurality of delay stages, and further includes a delay line control circuit coupled to the delay line circuit. The delay line control circuit is configured to enable delay stages of the plurality of delay stages, and is further configured to control enabled delay stages of the plurality of delay stages to provide a respective output clock signal having a high logic level during an idle state.
Abstract translation: 在空闲状态期间，可以通过装置和方法来控制延迟电路，以减少电气特性的劣化。 一种示例性装置包括包括多个延迟级的延迟线电路，并且还包括耦合到延迟线电路的延迟线控制电路。 延迟线控制电路被配置为启用多个延迟级的延迟级，并且还被配置为控制多个延迟级的使能的延迟级，以在空闲状态期间提供具有高逻辑电平的相应输出时钟信号。
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公开(公告)号：US20150109036A1
公开(公告)日：2015-04-23
申请号：US14058092
申请日：2013-10-18
Applicant: Micron Technology, Inc.
Inventor： Tyler J. Gomm , Yasuo Satoh
CPC classification number: H03K3/017 , H03K5/1565 , H03L7/06
Abstract: Methods and apparatuses are disclosed for preserving duty cycle at voltage domain boundaries. One example apparatus includes a complement generation circuit configured to generate a complementary signal responsive to an input signal. The complement generation circuit is configured to operate in a first voltage domain. The apparatus also includes a compensation circuit configured to generate a compensated signal by compensating the input signal for a delay corresponding to the complement generation circuit. The compensation circuit is configured to operate in a second voltage domain. The apparatus also includes a phase mixing circuit configured to combine the complementary signal and the compensated signal to generate an output signal.
Abstract translation: 公开了用于在电压域边界处保持占空比的方法和装置。 一个示例性装置包括补码生成电路，其被配置为响应于输入信号产生互补信号。 补码生成电路被配置为在第一电压域中操作。 该装置还包括补偿电路，其被配置为通过对与补码生成电路相对应的延迟补偿输入信号来产生补偿信号。 补偿电路被配置为在第二电压域中操作。 该装置还包括相位混合电路，该相位混合电路被配置为组合互补信号和经补偿的信号以产生输出信号。
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公开(公告)号：US08963604B2
公开(公告)日：2015-02-24
申请号：US14246328
申请日：2014-04-07
Applicant: Micron Technology, Inc.
Inventor： Eric Booth , Tyler J. Gomm , Kallol Mazumder , Scott E. Smith , John F. Schreck
Abstract: Circuits, integrated circuits, and methods are disclosed for bimodal disable circuits. In one such example method, a counter is maintained, with the counter indicating a logic level at which an output signal will be disabled during at least a portion of one of a plurality of disable cycles. The logic level indicated by the counter is transitioned. An input signal is provided as the output signal responsive to the enable signal indicating that the output signal is to be enabled, and the output signal is disabled at the logic level indicated by the counter responsive to the enable signal indicating that the output signal is to be disabled.
Abstract translation: 公开了用于双模禁止电路的电路，集成电路和方法。 在一个这样的示例性方法中，维持计数器，其中计数器指示在多个禁用周期中的至少一个的至少一部分期间输出信号将被禁用的逻辑电平。 由计数器指示的逻辑电平转换。 响应于指示输出信号被使能的使能信号，输出信号被提供作为输出信号，并且输出信号在由计数器指示的逻辑电平处被禁用，响应于使能信号，指示输出信号为 被禁用
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