公开(公告)号：US07636253B2

公开(公告)日：2009-12-22

申请号：US12354867

申请日：2009-01-16

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

摘要翻译： 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US07595893B2

公开(公告)日：2009-09-29

申请号：US11898865

申请日：2007-09-17

申请人： Sotomitsu Hara ,  Yutaka Tsuchida ,  Yoshikazu Arai ,  Yasushi Ishii ,  Makoto Abe ,  Yasushi Ueshima

发明人： Sotomitsu Hara ,  Yutaka Tsuchida ,  Yoshikazu Arai ,  Yasushi Ishii ,  Makoto Abe ,  Yasushi Ueshima

IPC分类号： G01B11/30 ,  G01B11/24

CPC分类号： G01B11/2408 ,  G01B11/2433

摘要： A shape measurement method for measuring a shape of an object to be measured, which has a substantially rotating symmetric shape, includes: placing an aperture having an opening larger than an outer shape of the object to be measured and the object to be measured on an optical axis; taking an image generated by light projected to the object to be measured, by using an image pickup unit; and calculating one cross-sectional shape of the object to be measured based on a light intensity distribution of the image taken by the image pickup unit.

摘要翻译： 一种用于测量被测物体的形状的形状测量方法，该形状测量方法具有基本上旋转的对称形状，包括：将具有大于被测量物体的外形的开口和被测量物体放置在 光轴; 通过使用图像拾取单元拍摄由投射到待测量对象的光产生的图像; 并且基于由图像拾取单元拍摄的图像的光强度分布来计算待测对象的一个​​横截面形状。

公开(公告)号：US20070262382A1

公开(公告)日：2007-11-15

申请号：US11727591

申请日：2007-03-27

申请人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

发明人： Yasushi Ishii ,  Takashi Hashimoto ,  Yoshiyuki Kawashima ,  Koichi Toba ,  Satoru Machida ,  Kozo Katayama ,  Kentaro Saito ,  Toshikazu Matsui

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/6653

摘要： In a semiconductor device which includes a split-gate type memory cell having a control gate and a memory gate, a low withstand voltage MISFET and a high withstand voltage MISFET, variations of the threshold voltage of the memory cell are suppressed. A gate insulating film of a control gate is thinner than a gate insulating film of a high withstand voltage MISFET, the control gate is thicker than a gate electrode 14 of the low withstand voltage MISFET and the ratio of thickness of a memory gate with respect to the gate length of the memory gate is larger than 1. The control gate and a gate electrode 15 are formed in a multilayer structure including an electrode material film 8A and an electrode material layer 8B, and the gate electrode 14 is a single layer structure formed at the same time as the electrode material film 8A of the control gate.

摘要翻译： 在包括具有控制栅极和存储器栅极的分离栅极型存储单元，低耐压MISFET和高耐压MISFET的半导体器件中，抑制了存储单元的阈值电压的变化。 控制栅极的栅极绝缘膜比高耐压MISFET的栅极绝缘膜薄，控制栅极比低耐压MISFET的栅电极14厚，存储栅的厚度比相对于 存储器栅极的栅极长度大于1.控制栅极和栅极电极15形成为包括电极材料膜8A和电极材料层8B的多层结构，并且栅电极14是单层 结构与控制门的电极材料膜8A同时形成。

公开(公告)号：US20070215930A1

公开(公告)日：2007-09-20

申请号：US11700865

申请日：2007-02-01

申请人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

发明人： Satoru Machida ,  Yasushi Ishii ,  Toshio Kudo ,  Masato Takahashi ,  Yukihiro Suzuki

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/42344

摘要： A memory cell has a control gate electrode disposed on a main surface of a semiconductor substrate through a gate insulating film, an ONO film disposed along a side surface of the control gate electrode and the main surface of semiconductor substrate, a memory gate electrode disposed on a side surface of the control gate electrode and also on the main surface of the semiconductor substrate through the ONO film. The control gate electrode and the memory gate electrode are formed, over the upper portions thereof, with a silicide film and an insulating film formed by oxidation of the surface of the silicide film, respectively.

摘要翻译： 存储单元具有通过栅极绝缘膜设置在半导体衬底的主表面上的控制栅极电极，沿着控制栅电极的侧表面和半导体衬底的主表面设置的ONO膜，设置在栅极绝缘膜上的存储栅电极 控制栅电极的侧表面以及通过ONO膜在半导体衬底的主表面上。 控制栅电极和存储栅电极在其上部分别形成有硅化物膜和通过硅化物膜的表面氧化形成的绝缘膜。

公开(公告)号：US20070201272A1

公开(公告)日：2007-08-30

申请号：US11797164

申请日：2007-05-01

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C16/04

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

摘要翻译： 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US6044421A

公开(公告)日：2000-03-28

申请号：US70773

申请日：1998-05-01

申请人： Yasushi Ishii

发明人： Yasushi Ishii

IPC分类号： G06F13/00 ,  G06F13/14 ,  H04L25/02 ,  H04L25/49

CPC分类号： G06F13/4273 ,  H04L25/0264 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A transmitting device and a receiving device are interconnected through two transmission paths, i.e. a data signal line for transmitting serial data, and a delimiting signal line for transmitting a delimiting signal. The delimiting signal causes the receiving device to recognize breaks between bits when the consecutive bits of the transmitted serial data have the same value. The level of the delimiting signal remains unchanged in the event of a change in the logical value of consecutive bits of the transmit data. The level of the delimiting signal is changed when consecutive bits of the transmit data have the same value. The receiving end, receiving the data signal and delimiting signal, reads as digital data the logical value of each bit in the data signal by regarding a point of time of a level change in either one of the data signal and delimiting signal as a break between bits.

摘要翻译： 发送装置和接收装置通过两条传输路径，即用于发送串行数据的数据信号线和用于发送定界信号的定界信号线相互连接。 当发送的串行数据的连续位具有相同的值时，定界信号使得接收设备识别位之间的中断。 在发送数据的连续位的逻辑值发生变化的情况下，定界信号的电平保持不变。 当发送数据的连续位具有相同的值时，定界信号的电平被改变。 接收端接收数据信号和定界信号，通过将数据信号和定界信号中的任何一个的电平变化的时间点作为数据信号和定界信号中的每个位的逻辑值作为数据信号， 位。

公开(公告)号：US09177937B2

公开(公告)日：2015-11-03

申请号：US12880399

申请日：2010-09-13

申请人： Masayuki Mochizuki ,  Yasushi Ishii

发明人： Masayuki Mochizuki ,  Yasushi Ishii

IPC分类号： H01L23/00 ,  H01L23/12

CPC分类号： H01L24/75 ,  F16F15/28 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01082 ,  H01L2924/014 ,  Y10T29/5313

摘要： The present invention aims to provide a lightened reaction absorber or to provide a semiconductor assembling system with further shorter processing time and high productivity or high quality using the lightened reaction absorber. The present invention is based upon a reaction absorber provided with a counter mechanism equipped with a load unit moved in a predetermined direction by a first ball screw, a second ball screw that generates reactive force in a reverse direction to the predetermined direction and a driving unit having a driving motor that drives the first ball screw and the second ball screw, and has a characteristic of including a reaction absorbing unit with one end side equipped with a nut connected to the second ball screw and the other end side fixed to a unit base movable relatively to the counter mechanism.

摘要翻译： 本发明的目的在于提供一种减轻反应吸收剂，或提供一种半导体组装体系，其使用更轻的反应吸收剂，具有更短的加工时间和高的生产率或高质量。 本发明是基于一种反应吸收器，该反应吸收器设置有一个配备有通过第一滚珠丝杠沿预定方向移动的载荷单元的反作用机构，产生与预定方向相反的方向产生反作用力的第二滚珠丝杠和驱动单元 具有驱动第一滚珠丝杠和第二滚珠丝杠的驱动马达，具有包括反应吸收单元的特性，该反应吸收单元的一端侧配备有连接到第二滚珠丝杠的螺母，另一端侧固定在单元基座 相对于计数器机构可移动。

公开(公告)号：US09093319B2

公开(公告)日：2015-07-28

申请号：US13468992

申请日：2012-05-10

申请人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

发明人： Kota Funayama ,  Hiraku Chakihara ,  Yasushi Ishii

IPC分类号： H01L29/94 ,  H01L27/115 ,  H01L27/105 ,  H01L21/28 ,  H01L49/02 ,  H01L29/423 ,  H01L29/792 ,  G11C16/04 ,  H01L29/66

CPC分类号： H01L27/11563 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/11565 ,  H01L27/11568 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/66477 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell of a nonvolatile memory and a capacitive element are formed over the same semiconductor substrate. The memory cell includes a control gate electrode formed over the semiconductor substrate via a first insulating film, a memory gate electrode formed adjacent to the control gate electrode over the semiconductor substrate via a second insulating film, and the second insulating film having therein a charge storing portion. The capacitive element includes a lower electrode formed of the same layer of a silicon film as the control gate electrode, a capacity insulating film formed of the same insulating film as the second insulating film, and an upper electrode formed of the same layer of a silicon film as the memory gate electrode. The concentration of impurities of the upper electrode is higher than that of the memory gate electrode.

摘要翻译： 在相同的半导体衬底上形成非易失性存储器和电容元件的存储单元。 存储单元包括经由第一绝缘膜形成在半导体衬底上的控制栅极电极，经由第二绝缘膜在半导体衬底上与控制栅电极相邻形成的存储栅电极，并且其中具有电荷存储的第二绝缘膜 一部分。 电容元件包括由与控制栅电极相同的硅膜层形成的下电极，由与第二绝缘膜相同的绝缘膜形成的电容绝缘膜和由相同的硅层形成的上电极 薄膜作为记忆栅电极。 上部电极的杂质浓度高于记忆栅电极的浓度。

公开(公告)号：US08969943B2

公开(公告)日：2015-03-03

申请号：US13302184

申请日：2011-11-22

申请人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

发明人： Koichi Toba ,  Yasushi Ishii ,  Hiraku Chakihara ,  Kota Funayama ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/792

摘要： A semiconductor device with a nonvolatile memory is provided which has improved characteristics. The semiconductor device includes a control gate electrode, a memory gate electrode disposed adjacent to the control gate electrode, a first insulating film, and a second insulating film including therein a charge storing portion. Among these components, the memory gate electrode is formed of a silicon film including a first silicon region positioned over the second insulating film, and a second silicon region positioned above the first silicon region. The second silicon region contains p-type impurities, and the concentration of p-type impurities of the first silicon region is lower than that of the p-type impurities of the second silicon region.

摘要翻译： 提供了具有非易失性存储器的半导体器件，其具有改进的特性。 半导体器件包括控制栅极电极，与控制栅电极相邻设置的存储栅电极，第一绝缘膜和包括电荷存储部分的第二绝缘膜。 在这些部件中，存储栅电极由包括位于第二绝缘膜上的第一硅区的硅膜和位于第一硅区之上的第二硅区构成。 第二硅区域含有p型杂质，第一硅区域的p型杂质浓度低于第二硅区域的p型杂质浓度。

公开(公告)号：US08431978B2

公开(公告)日：2013-04-30

申请号：US13587008

申请日：2012-08-16

申请人： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

发明人： Yoshiyuki Kawashima ,  Koichi Toba ,  Yasushi Ishii ,  Toshikazu Matsui ,  Takashi Hashimoto

IPC分类号： H01L27/08

CPC分类号： H01L28/60 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/105 ,  H01L27/10805 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  H01L28/40

摘要： In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.