公开(公告)号：US07494911B2

公开(公告)日：2009-02-24

申请号：US11527785

申请日：2006-09-27

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/00

CPC分类号： H01L29/7784 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02549 ,  H01L29/045 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66462

摘要： Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

摘要翻译： 各种实施例证明了在硅衬底上生长的缓冲层，其为相对于III-V材料器件层（例如基于InSb的器件）形成的器件以及在硅衬底上生长的体薄膜提供期望的隔离。 此外，缓冲层可以减轻晶体管器件和硅衬底之间的并联传导问题。 此外，缓冲层解决了薄膜相对于其形成晶体管和硅衬底之间的晶格失配。

公开(公告)号：US20080032478A1

公开(公告)日：2008-02-07

申请号：US11498901

申请日：2006-08-02

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/7785 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02549 ,  H01L21/02617 ,  H01L29/66462

摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

摘要翻译： 描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

公开(公告)号：US20120142166A1

公开(公告)日：2012-06-07

申请号：US13366143

申请日：2012-02-03

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02549 ,  H01L21/02617 ,  H01L29/66462

摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

摘要翻译： 描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×108cm-2的III-V InSb器件层。 在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

公开(公告)号：US07851781B2

公开(公告)日：2010-12-14

申请号：US12378407

申请日：2009-02-13

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

IPC分类号： H01L31/00

CPC分类号： H01L29/7784 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02549 ,  H01L29/045 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66462

摘要： Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

摘要翻译： 各种实施例提供了在硅衬底上生长的缓冲层，其为相对于III-V材料器件层（例如基于InSb的器件）形成的器件以及在硅衬底上生长的体薄膜提供期望的器件隔离。 此外，缓冲层可以减轻晶体管器件和硅衬底之间的并联传导问题。 此外，缓冲层解决了薄膜相对于其形成晶体管和硅衬底之间的晶格失配。

公开(公告)号：US07851780B2

公开(公告)日：2010-12-14

申请号：US11498685

申请日：2006-08-02

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Dmitri Loubychev ,  Amy W. K. Liu ,  Joel M. Fastenau

IPC分类号： H01L29/12

CPC分类号： H01L29/205 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/1029 ,  H01L29/812

摘要： A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

摘要翻译： 描述了用于在硅衬底上形成III-V器件层的复合缓冲结构及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的一个实施例中，双缓冲层位于III-V器件层和硅衬底之间以滑动位错并提供电隔离。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择每个缓冲层的材料，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施方式中，GaSb / AlSb缓冲器用于在硅衬底上形成基于InSb的量子阱晶体管。

公开(公告)号：US20080079003A1

公开(公告)日：2008-04-03

申请号：US11529974

申请日：2006-09-29

申请人： Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

发明人： Mohamad A. Shaheen ,  Peter Tolchinsky ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Suman Datta ,  David Simon

IPC分类号： H01L29/04 ,  H01L21/00

CPC分类号： H01L29/045 ,  H01L29/66795 ,  H01L29/7851

摘要： Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

摘要翻译： 本发明的实施例提供了具有在不同部分或区域中具有不同晶体取向的器件层的衬底。 具有一个晶体取向的一层材料可以结合到具有另一晶体取向的衬底。 然后，该层的一部分可以非晶化并退火，以再结晶到衬底的晶体取向。 可以在衬底上形成N型和P型器件，例如三栅极器件，每种类型的器件沿着所要求保护的区域的顶表面和侧表面具有适当的晶体取向，以获得最佳性能。 例如，衬底可以具有沿着NMOS三栅极晶体管的顶部和侧壁具有<100>晶体取向的部分，并且沿着PMOS三栅极的平行顶部和侧壁表面具有<110>晶体取向的另一部分 晶体管。

公开(公告)号：US20100072580A1

公开(公告)日：2010-03-25

申请号：US12620523

申请日：2009-11-17

申请人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Toichinsky

发明人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Toichinsky

IPC分类号： H01L29/04

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US07670928B2

公开(公告)日：2010-03-02

申请号：US11453444

申请日：2006-06-14

申请人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

发明人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US07355247B2

公开(公告)日：2008-04-08

申请号：US11072347

申请日：2005-03-03

申请人： Mohamad A. Shaheen ,  Kramadhati V. Ravi

发明人： Mohamad A. Shaheen ,  Kramadhati V. Ravi

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/16 ,  H01L21/0405 ,  H01L21/76254 ,  H01L29/1602 ,  H01L29/66742 ,  H01L29/78681

摘要： Embodiments of the invention provide substrate with an insulator layer on the substrate. The insulator layer may include diamond-like carbon. A device, such a tri-gate transistor may be formed on the diamond-like carbon layer.

摘要翻译： 本发明的实施例提供了在衬底上具有绝缘体层的衬底。 绝缘体层可以包括类金刚石碳。 可以在类金刚石碳层上形成三栅晶体管等器件。

公开(公告)号：US07148122B2

公开(公告)日：2006-12-12

申请号：US10925503

申请日：2004-08-24

申请人： Mohamad A. Shaheen ,  Ryan Z. Lei ,  Maxim B. Kelman

发明人： Mohamad A. Shaheen ,  Ryan Z. Lei ,  Maxim B. Kelman

IPC分类号： H01L21/30

CPC分类号： H01L21/306 ,  H01L21/187

摘要： In one embodiment, a method comprises placing a first and a second substrate into a reaction chamber, the first substrate being made of an indium antimonide material and having a first surface and the second substrate being made of a silicon or a silicon dioxide material and having a second surface; exposing the first and second surfaces to an oxygen plasma; forming a bond between the first and the second substrates by placing the first surface in contact with the second surface; and annealing the first and the second substrates to strengthen the bond.