公开(公告)号：US07670928B2

公开(公告)日：2010-03-02

申请号：US11453444

申请日：2006-06-14

申请人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

发明人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Tolchinsky

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US20100072580A1

公开(公告)日：2010-03-25

申请号：US12620523

申请日：2009-11-17

申请人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Toichinsky

发明人： Mohamad A. Shaheen ,  Willy Rachmady ,  Peter Toichinsky

IPC分类号： H01L29/04

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US20080132081A1

公开(公告)日：2008-06-05

申请号：US11633953

申请日：2006-12-04

申请人： Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

发明人： Mohamad A. Shaheen ,  Mantu K. Hudait ,  Willy Rachmady ,  Jack T. Kavalieros ,  Chris E. Barns

IPC分类号： H01L21/00

CPC分类号： H01L21/0254 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02549

摘要： A method of forming a thin III-V semiconductor film on a semiconductor substrate, where the lattice structure of the III-V film is different than the lattice structure of the substrate. The method includes epitaxially growing the III-V film on the substrate until the III-V film is greater than 3.0 μm thick and then removing a portion of the III-V film until it is less than 3.0 μm thick. In one implementation, the III-V film is grown until it is around 8.0 μm to 10.0 μm thick, and then it is etched or polished until its thickness is reduced to 0.1 μm to 3.0 μm thick. By over-growing the III-V film, effects such as dislocation gliding and annihilation reduce the dislocation density of the film, thereby improving its electric mobility.

摘要翻译： 在半导体衬底上形成薄的III-V半导体膜的方法，其中III-V膜的晶格结构不同于衬底的晶格结构。 该方法包括在衬底上外延生长III-V膜，直到III-V膜大于3.0μm厚，然后除去一部分III-V膜，直到其小于3.0μm厚。 在一个实施方案中，III-V膜生长直到其厚度约为8.0μm至10.0μm，然后进行蚀刻或抛光，直到其厚度减小至0.1μm至3.0μm厚。 通过过度生长III-V膜，如位错滑动和湮灭等作用降低了膜的位错密度，从而提高了其电迁移率。

公开(公告)号：US20080099839A1

公开(公告)日：2008-05-01

申请号：US11453444

申请日：2006-06-14

申请人： Willy Rachmady ,  Peter Tolchinsky

发明人： Willy Rachmady ,  Peter Tolchinsky

IPC分类号： H01L27/12 ,  H01L27/01 ,  H01L31/0392 ,  H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/76251 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01021 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A multi-layered substrate with bulk substrate characteristics and processes for the fabrication of such substrates are herein disclosed. The multi-layered substrate can include a first layer, a second layer and an interfacial layer therebetween. The first and second layers can be silicon, germanium, or any other suitable material of the same or different crystal orientations. The interfacial layer can be an oxide layer from about 5 Angstroms to about 50 Angstroms.

摘要翻译： 本文公开了具有体基板特性的多层基板和用于制造这种基板的工艺。 多层基板可以包括第一层，第二层和它们之间的界面层。 第一层和第二层可以是硅，锗或具有相同或不同晶体取向的任何其它合适的材料。 界面层可以是约5埃至约50埃的氧化物层。

公开(公告)号：US20230090092A1

公开(公告)日：2023-03-23

申请号：US17448382

申请日：2021-09-22

申请人： Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

发明人： Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

IPC分类号： H01L27/12 ,  H01L21/84

摘要： An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

公开(公告)号：US20210202476A1

公开(公告)日：2021-07-01

申请号：US16728983

申请日：2019-12-27

申请人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC分类号： H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US09590089B2

公开(公告)日：2017-03-07

申请号：US13997162

申请日：2011-12-30

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jack T. Kavalieros ,  Robert S. Chau ,  Seung Hoon Sung

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786 ,  B82Y10/00 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858 ,  Y10S977/762 ,  Y10S977/89 ,  Y10S977/938

摘要： Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

摘要翻译： 本文描述了具有一个或多个活性纳米线和一个或多个非活性纳米线的基于纳米线的栅极全周极晶体管器件。 还描述了制造这种装置的方法。 本发明的一个或多个实施例涉及用于改变包括具有不同数量的纳米线的纳米线堆叠的晶体管结构的栅极宽度的方法。 这些方法包括使一定数量的纳米线无效（即使得电流不流过纳米线），通过切断沟道区，掩埋源区和漏区，或两者。 总之，具有多个纳米线的纳米线基结构的栅极宽度可以通过使一定数量的纳米线无效而保持其它纳米线作为活性而变化。

公开(公告)号：US09159787B2

公开(公告)日：2015-10-13

申请号：US14301281

申请日：2014-06-10

申请人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

发明人： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Jessica S. Kachian ,  Marc C. French ,  Aaron A. Budrevich

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02584 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/365 ,  H01L29/42392 ,  H01L29/511 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/786 ,  H01L29/78696 ,  Y02E10/50

摘要： Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.

摘要翻译： 在那里制造的半导体器件堆叠和器件具有富锗器件层。 富锗器件层设置在衬底之上，其中设置有p型掺杂Ge蚀刻抑制层（例如，p型SiGe），以在去除牺牲半导体层期间抑制富锗器件层的蚀刻 Si比设备层更丰富。 随着在半导体膜堆叠中引入掩埋的p型掺杂半导体层，可以显着降低Ge在湿蚀刻剂（例如氢氧化物水溶液）中的溶解速率，从而提高蚀刻剂对Ge富集器件层的选择性。

公开(公告)号：US20150060945A1

公开(公告)日：2015-03-05

申请号：US14535387

申请日：2014-11-07

申请人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

发明人： Anand S. Murthy ,  Glenn A. Glass ,  Tahir Ghani ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Roza Kotlyar ,  Willy Rachmady ,  Mark Y. Liu

IPC分类号： H01L29/36 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08

CPC分类号： H01L29/0676 ,  H01L21/02532 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/3215 ,  H01L21/76831 ,  H01L23/535 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0615 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66681 ,  H01L29/66931 ,  H01L29/7785 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7833 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

摘要翻译： 公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。 在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。 在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。 可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。 锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。 这些技术可以例如在平面或非平面晶体管器件中实现。

公开(公告)号：US08883573B2

公开(公告)日：2014-11-11

申请号：US13563456

申请日：2012-07-31

申请人： Uday Shah ,  Benjamin Chu-Kung ,  Been-Yih Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

发明人： Uday Shah ,  Benjamin Chu-Kung ,  Been-Yih Jin ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Willy Rachmady

IPC分类号： H01L21/335 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/762 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696 ,  H01L2221/1094

摘要： The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

摘要翻译： 本公开涉及制造微电子器件的领域。 在至少一个实施方案中，本公开涉及形成分离的纳米线，其中与纳米线相邻的隔离结构提供用于在其上形成微电子结构的基本水平的表面。