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    MOUNTING SUBSTRATE
    11.
    发明申请
    MOUNTING SUBSTRATE 有权

    公开(公告)号：US20180040428A1

    公开(公告)日：2018-02-08

    申请号：US15669038

    申请日：2017-08-04

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

    IPC: H01G4/38 ,  H01G4/248 ,  H05K1/18 ,  H01G4/30 ,  H01G4/012

    CPC classification number: H01G4/38 ,  H01G2/06 ,  H01G4/012 ,  H01G4/232 ,  H01G4/248 ,  H01G4/30 ,  H01G4/308 ,  H05K1/0295 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10522

    Abstract: A mounting substrate on which at least any one of three kinds of electronic components including a first electronic component, a second electronic component, and a third electronic component are able to be mounted includes a pair of first edge portions and a pair of second edge portions. When a dimension of the first electronic component in its length direction is designated as L1, a dimension of the first electronic component in its width direction is designated as W1, a dimension of the second electronic component in its length direction is designated as L2, and a dimension of the second electronic component in its width direction is designated as W2, a dimension of the third electronic component in its width direction is any one of W1 and W2, and a dimension of the third electronic component in its length direction is L2 when the dimension of the third electronic component in its width direction is W1, and is L1 when the dimension of the third electronic component in its width direction is W2. At least one or more of the third electronic components are mounted on the mounting substrate.

    MULTILAYER CERAMIC CAPACITOR
    12.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 有权

    公开(公告)号：US20250037939A1

    公开(公告)日：2025-01-30

    申请号：US18913062

    申请日：2024-10-11

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Akito MORI ,  Masahiro WAKASHIMA ,  Sho WATANABE ,  Takumi ENDOU

    IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12

    Abstract: A multilayer ceramic capacitor includes a multilayer body including an inner layer portion including internal electrode layers and inner dielectric layers laminated alternately, and internal electrode layers at both ends thereof in a lamination direction, and outer dielectric layers covering the inner layer portion, and two external electrodes on both end surfaces of the multilayer body in a length direction intersecting the lamination direction. The inner and outer dielectric layers each include grains, and a difference between an average grain size of grains in the inner dielectric layers and an average grain size of grains in the outer dielectric layers is about 100 nm or less.

    MULTILAYER CERAMIC CAPACITOR
    17.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 有权

    公开(公告)号：US20210020377A1

    公开(公告)日：2021-01-21

    申请号：US16925350

    申请日：2020-07-10

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Yuta KUROSU ,  Masahiro WAKASHIMA

    IPC: H01G4/30 ,  H01G2/06 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12

    Abstract: A multilayer ceramic capacitor includes a ceramic multilayer body including ceramic layers and internal electrodes that are layered, main surfaces, side surfaces, and end surfaces, a conductor layer covering each of the end surfaces of the ceramic multilayer body and electrically connected to the internal electrodes, an insulating layer covering the conductor layer, and an external electrode electrically connected to the conductor layer. The conductor layer includes a portion that extends to a portion of each of the main surfaces of the ceramic multilayer body.

    MULTILAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    18.
    发明申请
    MULTILAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20190385793A1

    公开(公告)日：2019-12-19

    申请号：US16549088

    申请日：2019-08-23

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Masahiro WAKASHIMA

    IPC: H01G4/012 ,  H01G4/30 ,  H01G4/232

    Abstract: A multilayer ceramic capacitor includes a laminated body including dielectric layers and internal electrode layers alternately laminated in a width direction, and first and second external electrodes on a bottom surface of the laminated body. Among ridges located on a side of an upper surface of the laminated body of an inner layer generating capacitance, a ridge located on the side of a first end surface is a first ridge, and a ridge located on the side of a second end surface is a second ridge. When r1 is a curvature radius of the first ridge at a central position in the width direction of the laminated body, and r2 is a curvature radius of the second ridge at the central position in the width direction of the laminated body, conditions of r1≤50 μm and r2≤50 μm are satisfied.

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