公开(公告)号：US20110024824A1

公开(公告)日：2011-02-03

申请号：US12820351

申请日：2010-06-22

申请人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

发明人： Yasuhiro SHIMURA ,  Takashi Izumida ,  Mutsuo Morikado ,  Kiyomi Naruke

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/42324 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer and a transistor. The transistor includes: a source region, a drain region, and a channel region provided in the semiconductor layer, the channel region being between the source and drain regions; a gate insulating film provided on the channel region; a charge layer provided on the gate insulating film, the charge layer having a side portion and a apical portion;an inter-electrode insulating film covering the side portion and the apical portion; and a control gate provided on the inter-electrode insulating film. The control gate includes: a side-portion conductive layer opposing the side portion; and an apical-portion conductive layer opposing the apical portion.The apical-portion conductive layer has a work function higher than a work function of the charge layer and higher than a work function of the side-portion conductive layer.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括半导体层和晶体管。 晶体管包括：源极区，漏极区和设置在半导体层中的沟道区，沟道区位于源区和漏区之间; 设置在沟道区上的栅极绝缘膜; 设置在所述栅极绝缘膜上的电荷层，所述电荷层具有侧部和顶部; 覆盖所述侧部和所述顶部的电极间绝缘膜; 以及设置在电极间绝缘膜上的控制栅极。 控制门包括：与侧部相对的侧部导电层; 以及与顶端部分相对的顶端部导电层。 顶部导电层的功函数高于电荷层的功函数，高于侧面导电层的功函数。

公开(公告)号：US20100322009A1

公开(公告)日：2010-12-23

申请号：US12817665

申请日：2010-06-17

申请人： Takeshi SHIMANE ,  Naoyuki Shigyo ,  Mutsuo Morikado

发明人： Takeshi SHIMANE ,  Naoyuki Shigyo ,  Mutsuo Morikado

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0483 ,  G11C16/10

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate, memory cells without a source region and a drain region, and a first insulating film. The memory cells are arranged adjacent to one another on the semiconductor substrate and include a first gate electrode including a charge accumulation layer. A current path functioning as a source region or a drain region of a selected memory cell is formed in the semiconductor substrate when a voltage is applied to the first gate electrode of one of unselected memory cells. The first insulating film is formed on the semiconductor substrate to fill a region between the first gate electrodes of the memory cells adjacent to each other.

摘要翻译： 根据一个实施例，半导体存储器件包括半导体衬底，没有源极区和漏极区的存储单元和第一绝缘膜。 存储单元在半导体衬底上彼此相邻地布置，并且包括包括电荷累积层的第一栅电极。 当向未选择的存储单元之一的第一栅电极施加电压时，在半导体衬底中形成用作所选存储单元的源极区或漏极区的电流路径。 第一绝缘膜形成在半导体衬底上以填充彼此相邻的存储单元的第一栅电极之间的区域。

公开(公告)号：US20070013007A1

公开(公告)日：2007-01-18

申请号：US11485278

申请日：2006-07-13

申请人： Naoki Kusunoki ,  Mutsuo Morikado

发明人： Naoki Kusunoki ,  Mutsuo Morikado

IPC分类号： H01L29/76

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

摘要： A semiconductor device, comprising: a substrate; a floating body region formed in the substrate, a gate electrode formed above a first surface region of the floating body region via a gate insulating film, the gate electrode being connected to a word line; and source and drain regions, respectively, formed on second and third surface regions of the floating body region, the source region being connected to a source line and providing a first electric capacity at an interface relative to the floating body region, the drain region being connected to a bit line and providing a second electric capacity at an interface relative to the floating body region, the second electric capacity being smaller than the first electric capacity.

摘要翻译： 一种半导体器件，包括：衬底; 形成在所述基板中的浮体区域，经由栅极绝缘膜形成在所述浮体区域的第一表面区域的上方的栅电极，所述栅电极与字线连接; 以及分别形成在所述浮体区域的第二和第三表面区域上的源极和漏极区域，所述源极区域连接到源极线并且在相对于所述浮体区域的界面处提供第一电容，所述漏极区域为 连接到位线，并在相对于浮体区域的界面处提供第二电容，第二电容小于第一电容。

公开(公告)号：US20060157785A1

公开(公告)日：2006-07-20

申请号：US11296311

申请日：2005-12-08

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L27/12

CPC分类号： H01L29/7841 ,  G11C11/4074 ,  G11C2211/4016 ,  H01L27/10802

摘要： According to the present invention, there is provided a semiconductor storage device having a memory cell, comprising: a buried electrode formed on a semiconductor substrate; a semiconductor layer formed on said buried electrode via a buried insulating film; a surface electrode formed on said semiconductor layer via an insulating film; a source region and drain region formed in the semiconductor layer on both sides of said surface electrode with a predetermined spacing therebetween; and a floating body formed between said source region and drain region, and which stores data in accordance with whether holes are stored in said floating body, wherein said buried electrode serves as a gate electrode, and said surface electrode serves as a plate electrode.

摘要翻译： 根据本发明，提供一种具有存储单元的半导体存储装置，包括：形成在半导体衬底上的掩埋电极; 通过掩埋绝缘膜在所述掩埋电极上形成的半导体层; 经由绝缘膜形成在所述半导体层上的表面电极; 在所述表面电极的两侧的半导体层中以预定间隔形成的源极区和漏极区; 以及浮置体，形成在所述源极区域和漏极区域之间，并且根据孔是否存储在所述浮体中而存储数据，其中所述掩埋电极用作栅电极，并且所述表面电极用作平板电极。

公开(公告)号：US5447884A

公开(公告)日：1995-09-05

申请号：US268378

申请日：1994-06-29

申请人： Paul M. Fahey ,  Erwin Hammerl ,  Herbert L. Ho ,  Mutsuo Morikado

发明人： Paul M. Fahey ,  Erwin Hammerl ,  Herbert L. Ho ,  Mutsuo Morikado

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/76 ,  H01L21/762

CPC分类号： H01L21/3105 ,  H01L21/76232 ,  Y10S148/05

摘要： A method of forming shallow trench isolation with a nitride liner layer for devices in integrated circuits solves a problem of recessing the nitride liner that led to unacceptable voids in the trench filler material by using a liner thickness of less than 5 nm. A densification step of a pyrogenic oxide anneal at 800.degree. C. not only drives out impurities and achieves the same density as a conventional argon anneal at 1000.degree. C., but also drastically reduces the thermal load.

摘要翻译： 用集成电路中的器件形成具有氮化物衬垫层的浅沟槽隔离层的方法解决了通过使用小于5nm的衬里厚度而导致在沟槽填充材料中导致不可接受的空隙的氮化物衬垫的凹陷的问题。 在800℃下进行热解氧化退火的致密化步骤不仅驱除杂质，并且在1000℃下实现与常规氩退火相同的密度，而且显着降低热负荷。

公开(公告)号：US08541285B2

公开(公告)日：2013-09-24

申请号：US13191991

申请日：2011-07-27

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L21/76

CPC分类号： H01L27/11529 ,  H01L27/105 ,  H01L27/11526

摘要： According to an aspect of the present invention, there is provided a semiconductor memory device including: a semiconductor substrate having: first device regions divided by first isolation films and second device regions divided by second isolation films a gate insulating film formed on the semiconductor substrate; a first element including: a first gate formed on the gate insulating film in the first device regions, a first inter-electrode insulating film formed on the first gate and on the first isolation films, and a second gate formed on the first inter-electrode insulating film; and a second element including: a third gate formed on the gate insulating film in the second device regions, and a fourth gate formed on the third gate and on the second isolation films; wherein a thickness of the third gate is larger than a thickness of the first gate.

摘要翻译： 根据本发明的一个方面，提供了一种半导体存储器件，包括：半导体衬底，具有：由第一隔离膜和由第二隔离膜划分的第二器件区域划分的第一器件区域，形成在半导体衬底上的栅极绝缘膜; 第一元件，包括：形成在第一器件区域中的栅极绝缘膜上的第一栅极，形成在第一栅极和第一隔离膜上的第一电极间绝缘膜，以及形成在第一电极上的第二栅极 绝缘膜; 以及第二元件，包括：形成在第二器件区域中的栅极绝缘膜上的第三栅极和形成在第三栅极和第二隔离膜上的第四栅极; 其中所述第三栅极的厚度大于所述第一栅极的厚度。

公开(公告)号：US08154069B2

公开(公告)日：2012-04-10

申请号：US11845376

申请日：2007-08-27

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor memory includes a memory cell string having a plurality of memory cell transistors connected in series, a selection gate transistor connected in series with one end of the memory cell string, and having a gate electrode provided on a gate insulating film on a semiconductor substrate, and an element isolation insulating layer which is provided in the semiconductor substrate. The gate electrode includes a first gate electrode provided on the gate insulating film, a first and second insulating films provided on the first gate electrode, and a second gate electrode provided on the second insulating film and the element isolation insulating layer, and electrically connected to the first gate electrode. An first upper surface portion of the element isolation insulating layer below the second gate electrode is leveled with an upper surface of the first gate electrode.

摘要翻译： 非易失性半导体存储器包括具有串联连接的多个存储单元晶体管的存储单元串，与存储单元串的一端串联连接的选择栅极晶体管，并且具有设置在半导体上的栅极绝缘膜上的栅电极 衬底和设置在半导体衬底中的元件隔离绝缘层。 栅电极包括设置在栅极绝缘膜上的第一栅电极，设置在第一栅电极上的第一绝缘膜和第二绝缘膜，以及设置在第二绝缘膜和元件隔离绝缘层上的第二栅电极， 第一栅电极。 第二栅电极下方的元件隔离绝缘层的第一上表面部分与第一栅电极的上表面平齐。

公开(公告)号：US20110001180A1

公开(公告)日：2011-01-06

申请号：US12768086

申请日：2010-04-27

申请人： Kazunori MASUDA ,  Mutsuo Morikado ,  Kiyomi Naruke

发明人： Kazunori MASUDA ,  Mutsuo Morikado ,  Kiyomi Naruke

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： In a nonvolatile semiconductor memory device having a plurality of nonvolatile memory cells integrated on a semiconductor substrate, each of the memory cells includes a tunnel insulating film formed on the semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, a first interelectrode insulating film formed on the upper surface of the floating gate electrode, a second interelectrode insulating film formed to cover the side surfaces of the floating gate electrode and the first interelectrode insulating film, and a control gate electrode formed on the second interelectrode insulating film.

摘要翻译： 在具有集成在半导体基板上的多个非易失性存储单元的非易失性半导体存储器件中，每个存储单元包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的浮置栅电极，第一电极间绝缘膜 形成在浮栅电极的上表面上的膜，形成为覆盖浮栅和第一电极间绝缘膜的侧表面的第二电极间绝缘膜，以及形成在第二电极间绝缘膜上的控制栅电极。

公开(公告)号：US07583538B2

公开(公告)日：2009-09-01

申请号：US11691043

申请日：2007-03-26

申请人： Mutsuo Morikado ,  Tomoki Higashi

发明人： Mutsuo Morikado ,  Tomoki Higashi

IPC分类号： G11C11/03

CPC分类号： G11C11/4099 ,  G11C7/1015 ,  G11C7/14 ,  G11C11/406 ,  G11C11/409 ,  G11C2211/4016 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd>Vg−Vth0 holds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vth1 of said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vth0 of said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.

摘要翻译： 一种半导体存储器，包括在SOI衬底上形成的MOSFET的存储单元。 存储单元具有连接到字线的栅极电极，连接到位线的漏极区域和接地的源极区域。 读出写入存储单元的数据的操作是在施加到所述栅电极的栅极电压Vg与施加到所述漏极之间的漏极电压Vd之间的关系Vd> Vg-Vth0成立的偏置条件下执行的 区域，当在存储单元的体区中存储预定量的孔时，所述MOSFET的阈值电压Vth1，以及当量小于预定量的空穴存储在所述体区中时所述MOSFET的阈值电压Vth0 。

公开(公告)号：US07449375B2

公开(公告)日：2008-11-11

申请号：US11478742

申请日：2006-06-30

申请人： Mutsuo Morikado

发明人： Mutsuo Morikado

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L27/10829 ,  H01L21/84 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78609

摘要： A semiconductor device includes second to fourth semiconductor layers, a gate electrode, and an insulating film. The second semiconductor layer is formed on a first semiconductor layer and has a projecting shape. The third and fourth semiconductor layers are formed on the first semiconductor layer to be in contact with the second semiconductor layer and oppose each other via the second semiconductor layer. The gate electrode is in contact with the second semiconductor layer with a gate insulating film interposed therebetween and forms a channel in the second semiconductor layer. The insulating film is formed in the first semiconductor layer located immediately under the third and fourth semiconductor layers.

摘要翻译： 半导体器件包括第二至第四半导体层，栅电极和绝缘膜。 第二半导体层形成在第一半导体层上并具有突出形状。 第三和第四半导体层形成在第一半导体层上以与第二半导体层接触并且经由第二半导体层彼此相对。 栅电极与第二半导体层接触，栅极绝缘膜插入其间，并在第二半导体层中形成沟道。 绝缘膜形成在位于第三和第四半导体层正下方的第一半导体层中。