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公开(公告)号：US08854123B1
公开(公告)日：2014-10-07
申请号：US13946980
申请日：2013-07-19
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Brucek Kurdo Khailany , John W. Poulton , Thomas Hastings Greer, III , Carl Thomas Gray
CPC classification number: H05K1/11 , H04L25/028 , H04L25/0292
Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.
Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，第二处理器芯片和被配置为包括第一处理器芯片，第二处理器芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 在MCM封装内制造的第一组电迹线，用于将第一GRS接口电路耦合到互连电路。 第二处理器芯片被配置为包括第二GRS接口电路。 在MCM封装内制造的第二组电迹线，并被配置为将第二GRS接口电路耦合到互连电路。
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公开(公告)号：US11977766B2
公开(公告)日：2024-05-07
申请号：US17683292
申请日：2022-02-28
Applicant: NVIDIA Corporation
Inventor： William James Dally , Carl Thomas Gray , Stephen W. Keckler , James Michael O'Connor
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0679
Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.
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公开(公告)号：US11165394B2
公开(公告)日：2021-11-02
申请号：US16778895
申请日：2020-01-31
Applicant: Nvidia Corporation
Inventor： Sanquan Song , John Poulton , Carl Thomas Gray
Abstract: The disclosure provides an improved transimpedance amplifier (TIA) that can operate at a higher bandwidth and lower noise compared to conventional TIAs. The TIA employs a data path with both feedback impedance and feedback capacitance for improved performance. The feedback impedance includes at least two resistors in series and at least one shunt capacitor, coupled between the at least two resistors, that helps to extend the circuit bandwidth and improve SNR at the same time. The capacitance value of the shunt capacitor can be selected based on both the bandwidth and noise. In one example, the TIA includes: (1) a biasing path, and (2) a data path, coupled to the biasing path, including multiple inverter stages and at least one feedback capacitance coupled across an even number of the multiple inverter stages. An optical receiver and a circuit having the TIA are also disclosed.
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公开(公告)号：US20170093403A1
公开(公告)日：2017-03-30
申请号：US14869759
申请日：2015-09-29
Applicant: NVIDIA Corporation
Inventor： John Michael Wilson , John W. Poulton , Matthew Rudolph Fojtik , Carl Thomas Gray
IPC: H03K19/0185
CPC classification number: H03K19/018528
Abstract: A balanced, charge-recycling repeater link is disclosed. The link includes a first set of segments operating in a first voltage domain and a second set of segments operating in a second voltage domain. The link is configured to transmit a first signal over at least one segment in the first set of segments and at least one other segment in the second set of segments. Each segment of the link includes at least one active circuit element configured to charge or discharge one or more corresponding interconnects within the link and a level shifter configured to shift the level of a signal on a last interconnect of the segment from the first voltage domain to the second voltage domain or the second voltage domain to the first voltage domain.
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公开(公告)号：US09251870B2
公开(公告)日：2016-02-02
申请号：US13857099
申请日：2013-04-04
Applicant: NVIDIA Corporation
Inventor： William J. Dally , John W. Poulton , Thomas Hastings Greer, III , Brucek Kurdo Khailany , Carl Thomas Gray
IPC: G11C11/40 , G11C7/00 , G11C11/41 , G11C7/10 , G11C11/4096
CPC classification number: G11C7/00 , G11C7/1057 , G11C7/1069 , G11C11/4096 , G11C11/41 , H01L2224/0401 , H01L2224/16145 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.
Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，高速缓冲存储器和封装。 第一处理单元包括第一接地参考单端信令（GRS）接口电路，第二处理单元包括第二GRS接口电路。 高速缓冲存储器包括第三和第四GRS接口电路。 该包装包括将第一GRS接口耦合到第三GRS接口并将第二GRS接口耦合到第四GRS接口的一个或多个电迹线，其中第一GRS接口电路，第二GRS接口，第三GRS接口和 第四GRS接口电路各自被配置为通过在一个迹线和地面网络之间放电电容器来沿着一个或多个电迹线的一个迹线发送脉冲。
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Patent Agency Ranking
公开(公告)号：US20140301134A1
公开(公告)日：2014-10-09
申请号：US13857099
申请日：2013-04-04
Applicant: NVIDIA CORPORATION
Inventor： William J. Dally , John W. Poulton , Thomas Hastings Greer, III , Brucek Kurdo Khailany , Carl Thomas Gray
CPC classification number: G11C7/00 , G11C7/1057 , G11C7/1069 , G11C11/4096 , G11C11/41 , H01L2224/0401 , H01L2224/16145 , H01L2224/16227 , H01L2924/15192 , H01L2924/15311
Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.
Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，高速缓冲存储器和封装。 第一处理单元包括第一接地参考单端信令（GRS）接口电路，第二处理单元包括第二GRS接口电路。 高速缓冲存储器包括第三和第四GRS接口电路。 该包装包括将第一GRS接口耦合到第三GRS接口并将第二GRS接口耦合到第四GRS接口的一个或多个电迹线，其中第一GRS接口电路，第二GRS接口，第三GRS接口和 第四GRS接口电路各自被配置为通过在一个迹线和地面网络之间放电电容器来沿着一个或多个电迹线的一个迹线发送脉冲。
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公开(公告)号：US20140269012A1
公开(公告)日：2014-09-18
申请号：US13938161
申请日：2013-07-09
Applicant: NVIDIA Corporation
Inventor： William J. Dally , John W. Poulton , Thomas Hastings Greer, III , Brucek Kurdo Khailany , Carl Thomas Gray
IPC: G11C11/4096
CPC classification number: G11C11/4096 , G11C7/1057 , G11C7/1069 , H04L25/0276
Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.
Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，系统功能芯片和被配置为包括第一处理器芯片和系统功能芯片的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 系统功能芯片被配置为包括第二GRS接口电路。 在MCM封装内制造第一组电迹线，并耦合到第一GRS接口电路和第二GRS接口电路。 第一GRS接口电路和第二GRS接口电路一起提供第一处理器芯片和系统功能芯片之间的通信通道。
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公开(公告)号：US20140266416A1
公开(公告)日：2014-09-18
申请号：US13946980
申请日：2013-07-19
Applicant: NVIDIA Corporation
Inventor： William J. Dally , Brucek Kurdo Khailany , John W. Poulton , Thomas Hastings Greer, III , Carl Thomas Gray
IPC: H05K1/11
CPC classification number: H05K1/11 , H04L25/028 , H04L25/0292
Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.
Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，第二处理器芯片和被配置为包括第一处理器芯片，第二处理器芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 在MCM封装内制造的第一组电迹线，用于将第一GRS接口电路耦合到互连电路。 第二处理器芯片被配置为包括第二GRS接口电路。 在MCM封装内制造的第二组电迹线，并被配置为将第二GRS接口电路耦合到互连电路。
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公开(公告)号：US20240411709A1
公开(公告)日：2024-12-12
申请号：US18810657
申请日：2024-08-21
Applicant: NVIDIA Corporation
Inventor： William James Dally , Carl Thomas Gray , Stephen W. Keckler , James Michael O'Connor
IPC: G06F13/16 , G11C8/12 , H03K19/1776
Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
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公开(公告)号：US20230315651A1
公开(公告)日：2023-10-05
申请号：US17709031
申请日：2022-03-30
Applicant: NVIDIA Corporation
Inventor： William James Dally , Carl Thomas Gray , Stephen W. Keckler , James Michael O'Connor
IPC: G06F13/16 , H03K19/1776 , G11C8/12
CPC classification number: G06F13/161 , G06F13/1689 , G06F13/1673 , H03K19/1776 , G11C8/12
Abstract: Embodiments of the present disclosure relate to application partitioning for locality in a stacked memory system. In an embodiment, one or more memory dies are stacked on the processor die. The processor die includes multiple processing tiles and each memory die includes multiple memory tiles. Vertically aligned memory tiles are directly coupled to and comprise the local memory block for a corresponding processing tile. An application program that operates on dense multi-dimensional arrays (matrices) may partition the dense arrays into sub-arrays associated with program tiles. Each program tile is executed by a processing tile using the processing tile's local memory block to process the associated sub-array. Data associated with each sub-array is stored in a local memory block and the processing tile corresponding to the local memory block executes the program tile to process the sub-array data.
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