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    Semiconductor magnetic field sensors
    11.
    发明授权
    Semiconductor magnetic field sensors 有权
    半导体磁场传感器

    公开(公告)号：US08981442B2

    公开(公告)日：2015-03-17

    申请号：US14108106

    申请日：2013-12-16

    Applicant: NXP B.V.

    Inventor： Victor Zieren ,  Anco Heringa ,  Olaf Wunnicke ,  Jan Slotboom ,  Robert Hendrikus Margaretha van Veldhoven ,  Jan Claes

    IPC: H01L29/82 ,  H01L43/02 ,  G01R33/06 ,  H01L29/735 ,  H01L29/861

    CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

    Abstract: A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.

    Abstract translation: 公开了一种半导体磁场传感器，其包括在衬底层顶部的半导体阱。 半导体阱包括第一集电区域和第二集电区域以及放置在第一集电区域和第二集电区域之间的电流发射区域。 半导体阱还包括第一MOS结构，其具有位于第一集电区和电流发射区之间的第一栅极端子和第二MOS结构，具有位于电流发射区和第二电流之间的第二栅极端 收集区域。 在操作中，第一栅极端子和第二栅极端子被偏置以增加第一电流和第二电流的偏转长度。 偏转长度垂直于由半导体磁场传感器的表面限定并平行于磁场的平面。

    SEMICONDUCTOR MAGNETIC FIELD SENSORS
    12.
    发明申请
    SEMICONDUCTOR MAGNETIC FIELD SENSORS 有权
    半导体磁场传感器

    公开(公告)号：US20140175528A1

    公开(公告)日：2014-06-26

    申请号：US14108106

    申请日：2013-12-16

    Applicant: NXP B.V.

    Inventor： Victor Zieren ,  Anco Heringa ,  Olaf Wunnicke ,  Jan Slotboom ,  Robert Hendrikus Margaretha van Veldhoven ,  Jan Claes

    IPC: H01L43/02

    CPC classification number: H01L43/02 ,  G01R33/066 ,  H01L29/735 ,  H01L29/82 ,  H01L29/8611

    Abstract: A semiconductor magnetic field sensor comprising a semiconductor well on top of a substrate layer is disclosed. The semiconductor well includes a first current collecting region and a second current collecting region and a current emitting region placed between the first current collecting region and the second current collecting region. The semiconductor well also includes a first MOS structure, having a first gate terminal, located between the first current collecting region and the current emitting region and a second MOS structure, having a second gate terminal, located between the current emitting region and the second current collecting region. In operation, the first gate terminal and the second gate terminal are biased for increasing a deflection length of a first current and of a second current. The deflection length is perpendicular to a plane defined by a surface of the semiconductor magnetic field sensor and parallel to a magnetic field.

    Abstract translation: 公开了一种半导体磁场传感器，其包括在衬底层顶部的半导体阱。 半导体阱包括第一集电区域和第二集电区域以及放置在第一集电区域和第二集电区域之间的电流发射区域。 半导体阱还包括第一MOS结构，其具有位于第一集电区和电流发射区之间的第一栅极端子和第二MOS结构，具有位于电流发射区和第二电流之间的第二栅极端 收集区域。 在操作中，第一栅极端子和第二栅极端子被偏置以增加第一电流和第二电流的偏转长度。 偏转长度垂直于由半导体磁场传感器的表面限定并平行于磁场的平面。

    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT
    14.
    发明申请
    TRANSISTOR AMPLIFIER CIRCUIT AND INTEGRATED CIRCUIT 审中-公开
    晶体管放大器电路和集成电路

    公开(公告)号：US20150145005A1

    公开(公告)日：2015-05-28

    申请号：US14542990

    申请日：2014-11-17

    Applicant: NXP B.V.

    Inventor： Viet Thanh Dinh ,  Tony Vanhoucke ,  Evelyne Gridelet ,  Anco Heringa ,  Jan Willem Slotboom ,  Dirk Klaassen

    IPC: H01L29/737 ,  H01L29/08 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06

    CPC classification number: H01L29/7371 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/735 ,  H01L29/7378 ,  H01L29/7809 ,  H01L29/7835

    Abstract: Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region) of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

    Abstract translation: 公开了具有第一导电类型的第一区域用于将电荷载体注入晶体管的第一区域和第二导电类型的横向延伸的第二区域的晶体管，其具有包括用于从晶体管排出所述电荷载流子的接触端子的部分，其中， 第一区域与第二区域通过限定与第一区域的第一pn结的第二导电类型的中间区域和与第二区域的第二pn结分离，其中横向延伸区域将第二pn结部分与第二pn结分离， 并且其中所述晶体管还包括具有所述第二导电类型的掺杂区域的衬底，所述掺杂区域沿着所述横向延伸的第二区域接触并延伸，以及另外的接触端子，其连接到所述掺杂区域，以从所述掺杂区域中排出少数电荷载流子 横向延伸的第二区域。 还公开了包括这种晶体管的放大器电路和IC。

    SEMICONDUCTOR DEVICE
    16.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20160043708A1

    公开(公告)日：2016-02-11

    申请号：US14802840

    申请日：2015-07-17

    Applicant: NXP B.V.

    Inventor： Anco Heringa ,  Erwin Hijzen ,  Radu Surdeanu

    IPC: H03K5/24 ,  H01L29/08 ,  H03K17/687 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/78 ,  H01L29/45

    CPC classification number: H03K5/2472 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/0642 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H03K17/6871 ,  H01L2924/00

    Abstract: A semiconductor device comprising: a substrate having: a first terminal region; a second terminal region; a first extension region that extends from the first terminal region towards the second terminal region; a second extension region that extends from the second terminal region towards the first terminal region; a channel region between the first and second extension regions; a gate conductor that overlies the channel region of the substrate, the gate conductor configured to control conduction in the channel region; a first control conductor that overlies at least a portion of the first extension region, the first control conductor configured to control conduction in the first extension region; and a second control conductor that overlies at least a portion of the second extension region, the second control conductor configured to control conduction in the second extension region, wherein the first and second control conductors are electrically isolated within the semiconductor device from the gate conductor.

    Abstract translation: 一种半导体器件，包括：衬底，具有：第一端子区域; 第二终端区域; 从所述第一端子区域朝向所述第二端子区域延伸的第一延伸区域; 从所述第二端子区域朝向所述第一端子区域延伸的第二延伸区域; 第一和第二延伸区域之间的沟道区域; 栅极导体，其覆盖在所述衬底的沟道区域上，所述栅极导体被配置为控制所述沟道区域中的导通; 第一控制导体，其覆盖在第一延伸区域的至少一部分上，第一控制导体被配置为控制第一延伸区域中的导通; 以及第二控制导体，其覆盖在所述第二延伸区域的至少一部分上，所述第二控制导体被配置为控制所述第二延伸区域中的导通，其中所述第一和第二控制导体在所述半导体器件内与所述栅极导体电隔离。

    Field plate assisted resistance reduction in a semiconductor device
    17.
    发明授权
    Field plate assisted resistance reduction in a semiconductor device 有权
    半导体器件中的场板辅助电阻降低

    公开(公告)号：US09142625B2

    公开(公告)日：2015-09-22

    申请号：US13651096

    申请日：2012-10-12

    Applicant: NXP B.V.

    Inventor： Anco Heringa ,  Gerhard Koops ,  Boni Kofi Boksteen ,  Alessandro Ferrara

    IPC: H01L21/02 ,  H01L29/40 ,  H01L29/78 ,  H01L29/786

    CPC classification number: H01L29/402 ,  H01L29/404 ,  H01L29/7835 ,  H01L29/78624

    Abstract: Embodiments of a semiconductor device, a circuit including a semiconductor device and a driver circuit, and a method for operating a semiconductor device are described. In one embodiment, a semiconductor device includes a substrate, a source region, a drain region, and a drain extension region formed in the substrate, and an insulation layer adjacent to the drain extension region. A gate layer and a field plate are formed one of within and on the insulation layer. The field plate is located adjacent to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage can be applied to the field plate independent from voltages applied to the gate layer and the source region. Other embodiments are also described.

    Abstract translation: 描述半导体器件，包括半导体器件和驱动器电路的电路的实施例以及用于操作半导体器件的方法。 在一个实施例中，半导体器件包括在衬底中形成的衬底，源极区，漏极区和漏极延伸区以及与漏极延伸区相邻的绝缘层。 绝缘层内部和之上形成栅极层和场板。 场板位于漏极延伸区域附近，并且与栅极层和源极区域电绝缘，使得电压可以独立于施加到栅极层和源极区域的电压施加到场板。 还描述了其它实施例。

    SEMICONDUCTOR DEVICE
    20.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150123241A1

    公开(公告)日：2015-05-07

    申请号：US14500889

    申请日：2014-09-29

    Applicant: NXP B.V.

    Inventor： Liang Yan ,  Roel Daamen ,  Anco Heringa ,  Erwin Hijzen

    IPC: H01L27/12 ,  H01L29/06 ,  H01L27/06 ,  H01L23/367

    CPC classification number: H01L27/1203 ,  H01L23/3677 ,  H01L27/0211 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7824 ,  H01L2924/0002 ,  H05K7/20 ,  H01L2924/00

    Abstract: An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.

    Abstract translation: 在具有多个单元电池的SOI功率器件中引入了集成散热器阵列，其可以用于降低温度上升，从而在器件区域上的所有单元电池获得更均匀的温度峰值，使得易于 可以避免故障，从而可以提高设备的安全工作面积。 此外，阵列牺牲了较少的器件面积，因此导致低Rdson。

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