公开(公告)号：US20160172243A1

公开(公告)日：2016-06-16

申请号：US14566761

申请日：2014-12-11

Applicant: NXP B.V.

Inventor： Sascha Moeller ,  Thomas Rohleder ,  Guido Albermann ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  B23K26/364 ,  B23K26/402 ,  B23K10/00 ,  B24C1/04 ,  H01L21/3065 ,  H01J37/31 ,  H01J37/305 ,  H01J37/302 ,  H01L21/263 ,  H01L21/268 ,  B23K26/06 ,  B23K26/14

CPC classification number: H01L21/78 ,  B23K10/006 ,  B23K26/0626 ,  B23K26/14 ,  B23K26/364 ,  B23K26/402 ,  B23K2103/56 ,  B24C1/045 ,  H01J37/3023 ,  H01J37/305 ,  H01J37/31 ,  H01L21/2633 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/67092

Abstract: One example discloses a system for wafer material removal, including: a wafer structures map, identifying a first device structure having a first location and a second device structure having a second location; a material removal controller, coupled to the structures map, and having a material removal beam power level output signal and a material removal beam on/off status output signal; wherein the material removal controller is configured to select a first material removal beam power level and a first material removal beam on/off status corresponding to the first location; and wherein the material removal controller is configured to select a second material removal beam power level and a second material removal beam on/off status corresponding to the second location. Another example discloses an article of manufacture comprises at least one non-transitory, tangible machine readable storage medium containing executable machine instructions for wafer material removal.

Abstract translation: 一个实例公开了一种用于晶片材料去除的系统，包括：晶片结构图，识别具有第一位置的第一器件结构和具有第二位置的第二器件结构; 材料去除控制器，耦合到结构图，并具有材料去除光束功率电平输出信号和材料去除光束开/关状态输出信号; 其中所述材料去除控制器被配置为选择对应于所述第一位置的第一材料去除束功率水平和第一材料去除束开/关状态; 并且其中所述材料去除控制器被配置为选择对应于所述第二位置的第二材料去除束功率水平和第二材料去除束开/关状态。 另一个实例公开了一种制品，其包括至少一个非暂时的，有形的机器可读存储介质，其包含用于晶片材料去除的可执行机器指令。

公开(公告)号：US09245804B2

公开(公告)日：2016-01-26

申请号：US13967084

申请日：2013-08-14

Applicant: NXP B.V.

Inventor： Christian Zenz ,  Hartmut Buenning ,  Leonardus Antonius Elisabeth Van Gemert ,  Tonny Kamphuis ,  Sascha Moeller

IPC: H01L21/44 ,  H01L21/82 ,  H01L21/782 ,  H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L23/488 ,  H01L21/50 ,  H01L21/56 ,  H01L21/683 ,  H01L29/06 ,  H01L23/00

CPC classification number: H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (θ) of tooling impact upon a vertical face the semiconductor device.

Abstract translation: 与示例性实施例一致，存在半导体器件，其中有源器件具有正面和背面; 总体厚度的半导体器件包括具有限定在前侧表面上的电路的有源器件，前侧表面具有区域。 有源器件的背面具有有源器件厚度的部分深度和大约部分深度的宽度的凹部，在垂直边缘处围绕有源器件的凹部。 在有源器件的背面具有厚度的保护层，该保护材料的面积大于第一区域并具有间隔距离。 垂直边缘具有填充与垂直边缘齐平的凹部的保护层。 保护材料的间隔距离是半导体器件厚度和在半导体器件的垂直面上的工具冲击的角度（＆amp;）的切线的函数。

公开(公告)号：US10410922B2

公开(公告)日：2019-09-10

申请号：US15440522

申请日：2017-02-23

Applicant: NXP B.V.

Inventor： Hartmut Buenning

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: A method of manufacturing a device with six-sided protected walls is disclosed. The method includes fabricating the plurality of devices on a wafer, forming a plurality of contact pads on each of the plurality of devices, cutting a first trench around each of the plurality of devices from a backside of the wafer with an active side having a plurality of contact pads facing down, applying a protective coating on the backside of the wafer thus filling the first trench with a protective material of the protective coating on the backside and cutting a second trench from the active side. The second trench extends to end of the first trench; The method further includes applying a protective layer on the active side including filling the second trench with the material of the protective coating on the active side thus making a wall through a combination of the first trench and the second trench, the wall fully filled with the material of the protective layer on the backside and the protective layer on the active side and singulating each of the plurality of devices by cutting through the wall substantially in middle across a thickness of the wafer.

公开(公告)号：US09847258B2

公开(公告)日：2017-12-19

申请号：US14871482

申请日：2015-09-30

Applicant: NXP B.V.

Inventor： Thomas Rohleder ,  Hartmut Buenning ,  Guido Albermann ,  Sascha Moeller ,  Martin Lapke

IPC: H01L21/00 ,  H01L23/544 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/311 ,  H01L21/66 ,  H01L27/04 ,  H01L23/528 ,  H01L21/78

CPC classification number: H01L21/82 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/67092 ,  H01L21/78 ,  H01L22/12 ,  H01L23/528 ,  H01L27/04

Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device from a wafer substrate, the wafer substrate having a top-side surface with a plurality of active device die separated by saw lanes and an opposite under-side surface. The method comprises coating the under-side surface of the wafer substrate with a resilient coating, locating the position of the saw lanes from the underside surface, blade dicing trenches in the resilient material to expose under-side bulk material in the position of saw lanes, and plasma etching through the trenches to remove the exposed under-side bulk material.

公开(公告)号：US09349645B2

公开(公告)日：2016-05-24

申请号：US14055188

申请日：2013-10-16

Applicant: NXP B.V.

Inventor： Martin Lapke ,  Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Heiko Backer

IPC: H01L21/00 ,  H01L21/78 ,  B28D5/00 ,  B28D1/22 ,  H01L21/683 ,  H01L21/30 ,  H01L21/46

CPC classification number: H01L21/78 ,  B28D1/221 ,  B28D5/0041 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68386 ,  Y10T225/287 ,  Y10T225/298

Abstract: An apparatus, device and method for wafer dicing is disclosed. In one example, the apparatus discloses: a wafer holding device having a first temperature; a die separation bar moveably coupled to the wafer holding device; and a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture an attachment material in response to movement with respect to the wafer holding device. In another example, the method discloses: receiving a wafer having an attachment material applied to one side of the wafer; placing the wafer in a holding device having a first temperature; urging a die separation bar toward the wafer; and cooling the attachment material to a second temperature, which is lower than the first temperature, until the attachment material fractures in response to the urging.

Abstract translation: 公开了一种用于晶片切割的装置，装置和方法。 在一个示例中，该装置公开了：具有第一温度的晶片保持装置; 可移动地联接到晶片保持装置的模具分离杆; 以及联接到所述设备并具有第二温度的冷却装置，其使得能够使所述模具分离杆响应于相对于所述晶片保持装置的运动而破坏附着材料。 在另一示例中，该方法公开了：接收具有施加到晶片一侧的附着材料的晶片; 将晶片放置在具有第一温度的保持装置中; 推动模具分离杆朝向晶片; 并将附着材料冷却至低于第一温度的第二温度，直到附着材料响应于推动而断裂。

公开(公告)号：US20160071770A1

公开(公告)日：2016-03-10

申请号：US14481051

申请日：2014-09-09

Applicant: NXP B.V.

Inventor： Guido Albermann ,  Sascha Moeller ,  Thomas Rohleder ,  Martin Lapke ,  Hartmut Buenning

IPC: H01L21/78 ,  H01L21/306 ,  H01L23/544 ,  H01L21/304

CPC classification number: H01L23/544 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Consistent with an example embodiment, a method for preparing integrated circuit (IC) device die from a wafer substrate having a front-side with active devices and a back-side, comprises mounting the front-side of the wafer onto protective foil. A laser is applied to saw lane areas on the backside of the wafer, at a first focus depth to define a modification zone; the modification zone defined at a pre-determined depth within active device boundaries and the active device boundaries defined by the saw lane areas. The protective foil is stretched to separate IC device die from one another and expose active device side-walls. With dry-etching of the active device side-walls, the modification zone is substantially removed.

Abstract translation: 与示例性实施例一致，从具有有源器件和背面的正面的晶片衬底制备集成电路（IC）器件管芯的方法包括将晶片的前侧安装到保护箔上。 在第一聚焦深度处将激光施加到晶片背面上的锯道区域以限定修改区域; 修改区域在活动设备边界内的预定深度和由锯道区域限定的活动设备边界中定义。 保护箔被拉伸以将IC器件管芯彼此分开并暴露有源器件侧壁。 通过对有源器件侧壁的干蚀刻，基本上去除了改质区。

公开(公告)号：US09196537B2

公开(公告)日：2015-11-24

申请号：US13967164

申请日：2013-08-14

Applicant: NXP B.V.

Inventor： Leonardus Antonius Elisabeth Van Gemert ,  Hartmut Buenning ,  Tonny Kamphuis ,  Sascha Moeller ,  Christian Zenz

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/78 ,  H01L21/301 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/782 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/782 ,  H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/31 ,  H01L23/3114 ,  H01L23/3178 ,  H01L23/488 ,  H01L23/49816 ,  H01L24/11 ,  H01L29/0657 ,  H01L2221/68336 ,  H01L2221/68377 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/11 ,  H01L2924/014

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) wafer; The wafer has a topside surface and an back-side surface, and a plurality of device die having electrical contacts on the topside surface. The method comprises back-grinding, to a thickness, the back-side surface the wafer. A protective layer of a thickness is molded onto the backside of the wafer. The wafer is mounted onto a sawing foil; along saw lanes of the plurality of device die, the wafer is sawed, the sawing occurring with a blade of a first kerf and to a depth of the thickness of the back-ground wafer. Again, the wafer is sawed along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf, the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer. The plurality of device die are separated into individual device die. Each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance from a vertical edge of the individual device die.

Abstract translation: 与示例性实施例一致，存在用于组装晶片级芯片尺寸处理（WLCSP）晶片的方法; 晶片具有顶侧表面和背面表面，以及在顶侧表面上具有电触头的多个器件裸片。 该方法包括对晶片的背面进行背面研磨至厚度。 在晶片的背面上模制厚度保护层。 将晶片安装在锯片上; 沿着多个器件裸片的锯条，晶片被锯切，锯切发生在第一切口的刀片和背面晶片厚度的深度上。 再次，晶片沿着多个器件裸片的锯条被锯切，锯切发生在第二切口的刀片上，第二切口比第一切口窄，并锯切到保护层厚度的深度。 将多个器件裸片分离为单个器件管芯。 每个单独的器件管芯在背面具有保护层，保护层具有与单独器件管芯的垂直边缘的间隔距离。

公开(公告)号：US08895363B2

公开(公告)日：2014-11-25

申请号：US13833906

申请日：2013-03-15

Applicant: NXP B.V.

Inventor： Hartmut Buenning ,  Sascha Moeller ,  Guido Albermann ,  Thomas Rohleder ,  Michael Zernack

IPC: H01L21/44 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/6836 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2224/94 ,  H01L2224/11

Abstract: Consistent with an example embodiment, there is a method for assembling a wafer level chip scale processed (WLCSP) device from a wafer substrate, the method comprises grinding the back-side of the wafer substrate to a prescribed thickness. A plurality of trenches is sawed along a plurality of device die boundaries on a back-side surface of the wafer, the trenches having a bevel profile. The plurality of trenches is etched until the bevel profile of the plurality of trenches is rounded.

Abstract translation: 与示例性实施例一致，存在从晶片衬底组装晶片级芯片级处理（WLCSP）器件的方法，该方法包括将晶片衬底的背面磨削至规定厚度。 多个沟槽沿着晶片的背面表面上的多个器件裸片边界锯切，沟槽具有斜面形状。 多个沟槽被蚀刻直到多个沟槽的斜面轮廓为圆形。