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    SEMICONDUCTOR SWITCH DEVICE AND METHOD
    12.
    发明申请
    SEMICONDUCTOR SWITCH DEVICE AND METHOD 审中-公开

    公开(公告)号：US20190019867A1

    公开(公告)日：2019-01-17

    申请号：US16002841

    申请日：2018-06-07

    Applicant: NXP B.V.

    Inventor： Mahmoud Shehab Mohammad Al-Sa'di ,  Petrus Hubertus Cornelis Magnee ,  Ihor Brunets ,  Jan Willem Slotboom ,  Tony Vanhoucke

    IPC: H01L29/10 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

    Abstract: A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.

    PUF method using and circuit having an array of bipolar transistors
    13.
    发明授权
    PUF method using and circuit having an array of bipolar transistors 有权

    公开(公告)号：US10132858B2

    公开(公告)日：2018-11-20

    申请号：US14307563

    申请日：2014-06-18

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Viet Nguyen

    IPC: G01R31/28 ,  G01R19/00 ,  G06F21/73 ,  G09C1/00 ,  H04L9/08 ,  H04L9/32

    Abstract: A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed.

    Method of manufacturing a bipolar transistor, bipolar transistor and integrated circuit
    19.
    发明授权
    Method of manufacturing a bipolar transistor, bipolar transistor and integrated circuit 有权
    制造双极晶体管，双极晶体管和集成电路的方法

    公开(公告)号：US09111987B2

    公开(公告)日：2015-08-18

    申请号：US14259550

    申请日：2014-04-23

    Applicant: NXP B.V.

    Inventor： Evelyne Gridelet ,  Johannes Donkers ,  Petrus Hubertus Cornelis Magnee ,  Viet Dinh ,  Tony Vanhoucke

    IPC: H01L21/331 ,  H01L27/082 ,  H01L29/70 ,  H01L29/732 ,  H01L29/40 ,  H01L29/66 ,  H01L29/737

    CPC classification number: H01L29/732 ,  H01L29/407 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378

    Abstract: Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material.

    Abstract translation: 与示例实施例一致，双极晶体管包括通过基极区域与衬底中的集电极区域垂直分离的发射极区域。 双极晶体管还包括电连接到发射极区的场板; 场板沿着基极区域从发射极区域延伸到集电极区域，并且场板通过间隔物与基极区域和集电极区域横向电绝缘。 间隔物包括电绝缘材料，其包括氮化硅层，并通过另外的电绝缘材料与衬底垂直电隔离。

    Semiconductor devices with a mixed crystal region
    20.
    发明授权
    Semiconductor devices with a mixed crystal region 有权

    公开(公告)号：US11018230B1

    公开(公告)日：2021-05-25

    申请号：US16723311

    申请日：2019-12-20

    Applicant: NXP B.V.

    Inventor： Tony Vanhoucke ,  Mahmoud Shehab Mohammad Al-Sa'di ,  Johannes Josephus Theodorus Marinus Donkers ,  Jan Willem Slotboom

    IPC: H01L29/165 ,  H01L29/737 ,  H01L29/868

    Abstract: An embodiment of a semiconductor device may include a semiconductor substrate, a first semiconductor region comprising a first material with a first polarity formed within the semiconductor substrate and a second semiconductor region comprising the first material with a second polarity formed within the semiconductor substrate and coupled to the first semiconductor region. In an embodiment, a semiconductor device may also include a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region, and a depletion region formed between the first semiconductor region and the second semiconductor region. The depletion region may include a mixed crystal region that includes a mixed crystal alloy of the first material and a second material, wherein the mixed crystal region has a lower bandgap energy than a bandgap energy of the first material.

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