公开(公告)号：US5780324A

公开(公告)日：1998-07-14

申请号：US605637

申请日：1996-02-22

申请人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

发明人： Norihito Tokura ,  Shigeki Takahashi ,  Tsuyoshi Yamamoto ,  Mitsuhiro Kataoka ,  Kunihiko Hara

IPC分类号： H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/332

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/4236

摘要： A manufacturing method of a vertical DMOSFET having a concave channel structure, which does not permit the introduction of defects or contaminant into the channel part and which can make the shape of the groove uniform, is disclosed. On a surface of a (100)-oriented n.sup.- -on-n.sup.+ epitaxial wafer is formed an initial groove by chemical dry etching. The grooved surface is then oxidized by LOCOS technique to form a LOCOS oxide film, whereby the concave structure is formed on the epitaxial wafer. The concave width is set to be at least twice the concave depth, and the sidewall angle is set to be approximately 50.degree. to make the sidewall plane (111) of high channel mobility plane. Following this process, p-type and n-type impurities are diffused from the main surface using the LOCOS oxide film as a double diffusion mask to form a body region and a source region.

摘要翻译： 公开了一种具有凹槽结构的垂直DMOSFET的制造方法，其不允许将缺陷或污染物引入通道部分并且可以使凹槽的形状均匀。 在（100）取向的n-on + n外延晶片的表面上，通过化学干蚀刻形成初始槽。 然后通过LOCOS技术将开槽的表面氧化以形成LOCOS氧化物膜，由此在外延晶片上形成凹形结构。 凹形宽度被设定为凹入深度的至少两倍，并且将侧壁角度设定为大约50°以使高通道迁移面的侧壁平面（111）。 在该过程之后，使用LOCOS氧化物膜作为双扩散掩模，从主表面扩散p型和n型杂质，以形成体区和源区。

公开(公告)号：US5460985A

公开(公告)日：1995-10-24

申请号：US30338

申请日：1993-03-25

申请人： Norihito Tokura ,  Shigeki Takahashi

发明人： Norihito Tokura ,  Shigeki Takahashi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8232

CPC分类号： H01L29/0696 ,  H01L21/28167 ,  H01L29/045 ,  H01L29/7813 ,  H01L21/28211 ,  H01L29/4236 ,  Y10S148/116 ,  Y10S148/126

摘要： A vertical type power MOSFET remarkably reduces its ON-resistance per area. A substantial groove formation in which a gate structure is constituted is performed beforehand utilizing the LOCOS method before the formation of a p-type base layer and an n.sup.+ -type source layer. The p-type base layer and the n.sup.+ -type source layer are then formed by double diffusion in a manner of self-alignment with respect to a LOCOS oxide film, simultaneously with which channels are set at sidewall portions of the LOCOS oxide film. Thereafter the LOCOS oxide film is removed to provide a U-groove so as to constitute the gate structure. Namely, the channels are set by the double diffusion of the manner of self-alignment with respect to the LOCOS oxide film, so that the channels, which are set at the sidewall portions at both sides of the groove, provide a structure of exact bilateral symmetry, there is no positional deviation of the U-groove with respect to the base layer end, and the length of the bottom face of the U-groove can be made minimally short. Therefore, the unit cell size is greatly reduced, and the ON-resistance per area is greatly decreased.

摘要翻译： PCT No.PCT / JP92 / 00929 Sec。 371日期1993年3月25日 102（e）1993年3月25日PCT提交1992年7月22日PCT公布。 公开号WO93 / 03502 日期：1993年2月18日。垂直型功率MOSFET显着降低了其面积的导通电阻。 在形成p型基极层和n +型源极层之前，利用LOCOS方法预先利用构成栅极结构的实质的槽形成。 然后通过相对于LOCOS氧化物膜的自对准的双扩散形成p型基极层和n +型源极层，同时将通道设置在LOCOS氧化物膜的侧壁部分。 此后，去除LOCOS氧化物膜以提供U形槽以构成栅极结构。 即，通过相对于LOCOS氧化膜的自对准方式的双扩散来设定通道，使得设置在凹槽两侧的侧壁部分处的通道提供精确双边的结构 U形槽相对于基底层端部没有位置偏离，U槽的底面的长度最短。 因此，单元电池尺寸大大降低，并且每个面积的导通电阻大大降低。

公开(公告)号：US4608958A

公开(公告)日：1986-09-02

申请号：US533812

申请日：1983-09-19

申请人： Yasuyuki Sakakibara ,  Norihito Tokura

发明人： Yasuyuki Sakakibara ,  Norihito Tokura

IPC分类号： F02D41/20 ,  F02D41/40 ,  F02P3/08 ,  F02P7/03 ,  F02P15/10

CPC分类号： F02P7/035 ,  F02D41/2096 ,  F02D41/40 ,  F02P15/10 ,  F02P3/0892 ,  F02D2041/2003 ,  Y02T10/44

摘要： A device for driving a load reactance element, such as a piezoelectric actuator for a fuel injection system, including a series reactance element connected in series with the load reactance element, and a resonance circuit formed by the load reactance and the series reactance. First and second switching elements are connected between the resonance circuit and the power source or ground potential. Each of the first and second switching elements is rendered conductive only during a half cycle of resonance. The directions of the load current flowing through the load reactance element are switchable by making alternately the first and second switching elements conductive.

摘要翻译： 用于驱动负载电抗元件的装置，例如用于燃料喷射系统的压电致动器，包括与负载电抗元件串联连接的串联电抗元件，以及由负载电抗和串联电抗形成的谐振电路。 第一和第二开关元件连接在谐振电路和电源或地电位之间。 第一和第二开关元件中的每一个仅在谐振的半周期期间才导通。 流过负载电抗元件的负载电流的方向可以通过交替地使第一和第二开关元件导通来切换。

公开(公告)号：US4584553A

公开(公告)日：1986-04-22

申请号：US617478

申请日：1984-06-05

申请人： Norihito Tokura ,  Hisasi Kawai

发明人： Norihito Tokura ,  Hisasi Kawai

IPC分类号： H01C7/00 ,  H01C17/23 ,  H01C1/01

CPC分类号： H01C17/23

摘要： A coated layer type resistor device having a first resistor element and a second resistor element. The ratio between the resistances of the first and second resistor elements is selected to be greater than a predetermined ratio. The first resistor element is formed on an insulator substrate and consists of a resistor layer and end conductor electrodes at the ends of the resistor layer, while the second resistor element is formed on the substrate and consists of a resistor layer, end conductor electrodes, and a plurality of intermediate conductors. The distance between adjacent ones of the intermediate conductors and the distance between one of the end conductor electrodes and the adjacent intermediate conductor in the second resistor element is equal to the distance between the end conductor electrodes in the first resistor element, so that the temperature coefficient property of the resistance is equal in both the first and second resistor elements.

摘要翻译： 一种具有第一电阻元件和第二电阻元件的涂层型电阻器件。 选择第一和第二电阻元件的电阻之比大于预定的比例。 第一电阻元件形成在绝缘体基板上，由电阻层和电阻层的端部的端部导体电极构成，第二电阻元件形成在基板上，由电阻层，端子导体电极和 多个中间导体。 相邻的中间导体之间的距离和第二电阻元件中的一个端子导体电极与相邻的中间导体之间的距离等于第一电阻元件中端部导体电极之间的距离，使得温度系数 电阻的性质在第一和第二电阻元件两者相等。

公开(公告)号：US08854033B2

公开(公告)日：2014-10-07

申请号：US13150764

申请日：2011-06-01

申请人： Satoshi Shiraki ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

发明人： Satoshi Shiraki ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

IPC分类号： G01R1/20

CPC分类号： H01L27/1203 ,  G01R19/0092 ,  H01L21/76283 ,  H01L23/585 ,  H01L29/0696 ,  H01L29/405 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.

摘要翻译： 具有横向半导体元件的半导体器件包括半导体衬底，衬底上的第一电极，衬底上的第二电极和位于衬底中的隔离结构，以将衬底分成第一岛和与第一岛电绝缘的第二岛 第一个岛屿。 横向半导体元件包括位于第一岛中的主单元和位于第二岛中的感测单元。 主电池使得第一电流在第一电极和第二电极之间流动，使得第一电流沿着基板的表面在横向方向上流动。 通过检测流过感测单元的第二电流来检测第一电流。

公开(公告)号：US20140048911A1

公开(公告)日：2014-02-20

申请号：US14113419

申请日：2012-05-10

申请人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

发明人： Takashi Suzuki ,  Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Youichi Ashida ,  Akira Yamada

IPC分类号： H01L29/06

CPC分类号： H01L29/063 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/861

摘要： A lateral semiconductor device includes a semiconductor layer, an insulating layer, and a resistive field plate. The semiconductor layer includes a first semiconductor region and a second semiconductor region at a surface portion, and the second semiconductor region makes a circuit around the first semiconductor region. The insulating layer is formed on a surface of the semiconductor layer and is disposed between the first and second semiconductor regions. The resistive field plate is formed on a surface of the insulating layer. Between the first and second semiconductor regions, a first section and a second section are adjacent to each other along a circumferential direction around the first semiconductor region. The resistive field plate includes first and second resistive field plate sections respectively formed in the first and second sections, and the first and second resistive field plate sections are separated from each other.

摘要翻译： 横向半导体器件包括半导体层，绝缘层和电阻场板。 半导体层包括在表面部分处的第一半导体区域和第二半导体区域，并且第二半导体区域在第一半导体区域周围形成电路。 绝缘层形成在半导体层的表面上并且设置在第一和第二半导体区之间。 电阻场板形成在绝缘层的表面上。 在第一和第二半导体区域之间，第一部分和第二部分沿着围绕第一半导体区域的圆周方向彼此相邻。 电阻场板包括分别形成在第一和第二部分中的第一和第二电阻场板部分，并且第一和第二电阻场板部分彼此分离。

公开(公告)号：US08476673B2

公开(公告)日：2013-07-02

申请号：US13296832

申请日：2011-11-15

申请人： Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

发明人： Norihito Tokura ,  Satoshi Shiraki ,  Shigeki Takahashi ,  Shinya Sakurai ,  Takashi Suzuki

IPC分类号： H01L29/861 ,  H01L29/747 ,  H01L31/107

CPC分类号： H01L21/76283 ,  H01L27/0814 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/405 ,  H01L29/8611

摘要： A diode has a semiconductor layer and cathode and anode electrodes on a surface of the semiconductor layer. The semiconductor layer has cathode and anode regions respectively contacting the cathode and anode electrodes. The anode region has a first diffusion region having high surface concentration, a second diffusion region having intermediate surface concentration, and a third diffusion region having low surface concentration. The first diffusion region is covered with the second and third diffusion regions. The second diffusion region has a first side surface facing the cathode region, a second side surface opposite to the cathode region, and a bottom surface extending between the first and second side surfaces. The third diffusion region covers at least one of the first corner part connecting the first side surface with the bottom surface and the second corner part connecting the second side surface with the bottom surface.

摘要翻译： 二极管在半导体层的表面上具有半导体层和阴极和阳极电极。 半导体层具有分别与阴极和阳极电极接触的阴极和阳极区域。 阳极区域具有表面浓度高的第一扩散区域，具有中间表面浓度的第二扩散区域和具有低表面浓度的第三扩散区域。 第一扩散区被第二和第三扩散区覆盖。 第二扩散区域具有面对阴极区域的第一侧表面，与阴极区域相对的第二侧表面和在第一和第二侧表面之间延伸的底表面。 第三扩散区域覆盖连接第一侧表面与底表面的第一角部和将第二侧表面与底表面连接的第二角部中的至少一个。

公开(公告)号：US20120032313A1

公开(公告)日：2012-02-09

申请号：US13197719

申请日：2011-08-03

申请人： Takao YAMAMOTO ,  Norihito Tokura ,  Hisato Kato ,  Akio Nakagawa

发明人： Takao YAMAMOTO ,  Norihito Tokura ,  Hisato Kato ,  Akio Nakagawa

IPC分类号： H01L29/861

CPC分类号： H01L29/868 ,  H01L27/0664 ,  H01L29/0615 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/7394 ,  H01L29/7824

摘要： A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.

摘要翻译： 具有横向二极管的半导体器件包括半导体层，半导体层中的第一半导体区域，具有大于第一半导体区域的杂质浓度的杂质浓度的接触区域，位于半导体层中并与该半导体层分离的第二半导体区域 接触区域，通过接触区域电连接到第一半导体区域的第一电极和与第二半导体区域电连接的第二电极。 第二半导体区域包括低杂质浓度部分，高杂质浓度部分和延伸部分。 第二电极与高杂质浓度部分形成欧姆接触。 延伸部分的杂质浓度大于低杂质浓度部分的杂质浓度，并且在半导体层的厚度方向上延伸。

公开(公告)号：US20110298446A1

公开(公告)日：2011-12-08

申请号：US13150764

申请日：2011-06-01

申请人： Satoshi SHIRAKI ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

发明人： Satoshi SHIRAKI ,  Norihito Tokura ,  Shigeki Takahashi ,  Masahiro Yamamoto ,  Akira Yamada ,  Hiroyasu Kudo ,  Youichi Ashida ,  Akio Nakagawa

IPC分类号： G01R1/20 ,  H01L29/739

CPC分类号： H01L27/1203 ,  G01R19/0092 ,  H01L21/76283 ,  H01L23/585 ,  H01L29/0696 ,  H01L29/405 ,  H01L29/7394 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.

摘要翻译： 具有横向半导体元件的半导体器件包括半导体衬底，衬底上的第一电极，衬底上的第二电极和位于衬底中的隔离结构，以将衬底分成第一岛和与第一岛电绝缘的第二岛 第一个岛屿。 横向半导体元件包括位于第一岛中的主单元和位于第二岛中的感测单元。 主电池使得第一电流在第一电极和第二电极之间流动，使得第一电流沿着基板的表面在横向方向上流动。 通过检测流过感测单元的第二电流来检测第一电流。

公开(公告)号：US20060289928A1

公开(公告)日：2006-12-28

申请号：US10573793

申请日：2004-10-06

申请人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

发明人： Hidefumi Takaya ,  Kimimori Hamada ,  Akira Kuroyanagi ,  Yasushi Okura ,  Norihito Tokura

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7397 ,  H01L29/7811

摘要： The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P− body region 41, and N− drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.

摘要翻译： 本发明旨在提供可以容易地制造的绝缘栅型半导体器件及其制造方法，同时实现更高的耐压设计和较低的导通电阻设计。 半导体器件包括N +源极区31，N +漏极区11，P-体区41和N漂移区12.通过挖掘半导体器件的上侧的一部分，形成栅沟槽21。 栅极沟槽21浮置区域51设置在栅极沟槽21的下方。可以形成与栅极沟槽21的深度不同的另外的沟槽35，P浮动区域54设置在沟槽25的下方。