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    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS
    11.
    发明申请
    COLUMN RAMP BUFFER DESIGN TO IMPROVE ADC RANGE IN CIS 有权

    公开(公告)号：US20250047995A1

    公开(公告)日：2025-02-06

    申请号：US18363473

    申请日：2023-08-01

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Liang Zuo ,  Hiroaki Ebihara ,  Jing Jun Yi ,  Rui Wang ,  Satoshi Sakurai

    IPC: H04N25/677 ,  H04N25/766 ,  H04N25/772

    Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

    Analog to digital converter clock control to extend analog gain and reduce noise
    12.
    发明授权
    Analog to digital converter clock control to extend analog gain and reduce noise 有权

    公开(公告)号：US11431939B1

    公开(公告)日：2022-08-30

    申请号：US17217935

    申请日：2021-03-30

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Lihang Fan ,  Nijun Jiang ,  Liang Zuo ,  Yuedan Li ,  Min Qu

    IPC: H04N5/378 ,  H03M1/18 ,  H04N5/357 ,  H03M1/12 ,  H03M3/00

    Abstract: A clock control circuit of an ADC includes a plurality of fractional divider circuits, each including a programmable integer divider coupled to receive an enable skew signal, a clock signal, and an output integer signal to divide down the clock signal by a factor responsive to the output integer signal to generate a fractional divider signal. A delta-sigma modulator is coupled to receive a fractional modulus signal, an input integer signal, and the fractional divider signal to generate the output integer signal, which is a varying signal each cycle and having a long term average DC value substantially equal to a fractional divider ratio K. An extended gain control circuit is coupled to receive the fractional divider signal from each of the fractional divider circuits to generate a plurality of ramp clock signals with adjustable frequencies to adjust a gain setting of a ramp generator of the ADC.

    IMAGE SENSOR WITH VOLTAGE SUPPLY GRID CLAMPING
    13.
    发明申请
    IMAGE SENSOR WITH VOLTAGE SUPPLY GRID CLAMPING 有权

    公开(公告)号：US20220078365A1

    公开(公告)日：2022-03-10

    申请号：US17531465

    申请日：2021-11-19

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Bi Yuan ,  Liang Zuo

    IPC: H04N5/378 ,  H04N5/3745 ,  H04N5/374 ,  H04N5/376 ,  H04N5/369

    Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

    IMAGE SENSOR WITH VOLTAGE SUPPLY GRID CLAMPING
    14.
    发明申请
    IMAGE SENSOR WITH VOLTAGE SUPPLY GRID CLAMPING 有权

    公开(公告)号：US20210176417A1

    公开(公告)日：2021-06-10

    申请号：US16708135

    申请日：2019-12-09

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Chengcheng Xu ,  Rui Wang ,  Bi Yuan ,  Liang Zuo

    IPC: H04N5/378 ,  H04N5/3745

    Abstract: An image sensing device includes an image sensing circuit, a voltage supply grid, bitlines, and a control circuit. The image sensing circuit includes pixels arranged in rows and columns. Each one of the bitlines is coupled to a corresponding one of the columns. The voltage supply grid is coupled to the pixels. The control circuit is coupled to output at least a row select signal and a transfer signal to the rows. Each one of the rows is selectively coupled to the bitlines to selectively output image data signals in response to the row select signal and the transfer signal. Each one of the rows is further selectively coupled to the bitlines to selectively clamp the bitlines in response to the row select signal and the transfer signal. Each one of the rows is selectively decoupled from the bitlines in response to the row select signal.

    INTEGRATING RAMP CIRCUIT WITH REDUCED RAMP SETTLING TIME
    15.
    发明申请
    INTEGRATING RAMP CIRCUIT WITH REDUCED RAMP SETTLING TIME 审中-公开

    公开(公告)号：US20200295739A1

    公开(公告)日：2020-09-17

    申请号：US16352673

    申请日：2019-03-13

    Applicant: OmniVision Technologies, Inc.

    Inventor： Liang Zuo ,  Rui Wang ,  Hiroaki Ebihara ,  Nijun Jiang

    IPC: H03K4/56 ,  H03F3/45 ,  H03M1/56 ,  H04N5/378 ,  H04N5/369 ,  H04N5/3745

    Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.

    Image sensor pixel noise measurement
    16.
    发明授权
    Image sensor pixel noise measurement 有权

    公开(公告)号：US09961281B2

    公开(公告)日：2018-05-01

    申请号：US15179648

    申请日：2016-06-10

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Bi Yuan ,  Liping Deng ,  Yingkan Lin ,  Liang Zuo ,  Yuxin Wang

    IPC: H04N5/357 ,  H04N5/378

    CPC classification number: H04N5/357 ,  H04N5/378

    Abstract: An image sensor pixel noise measurement circuit includes a pixel array on an integrated circuit chip. The pixel array includes a plurality of pixels including a first pixel to output a first image data signal, and a second pixel to output a second image data signal. A noise amplification circuit on the integrated circuit chip is coupled to receive the first and second image data signals from the pixel array. The noise amplification circuit is coupled to output an amplified differential noise signal in response to the first and second image data signals received from the pixel array. A fast Fourier transform (FFT) analysis circuit on the integrated circuit chip is coupled to transform the amplified differential noise signal output by the noise amplification circuit from a time domain to a frequency domain to analyze a pixel noise characteristic of the pixel array.

    Adaptive correlated multiple sampling
    17.
    发明授权
    Adaptive correlated multiple sampling 有权

    公开(公告)号：US12200389B2

    公开(公告)日：2025-01-14

    申请号：US18322408

    申请日：2023-05-23

    Applicant: OMNIVISION TECHNOLOGIES, INC.

    Inventor： Hiroaki Ebihara ,  Jiayu Guo ,  Liang Zuo ,  Lihang Fan

    IPC: H04N25/78 ,  H03K3/037 ,  H03K5/22 ,  H03K5/24 ,  H03K19/20 ,  H04N25/616

    Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

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