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公开(公告)号：US09819930B2
公开(公告)日：2017-11-14
申请号：US14721424
申请日：2015-05-26
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tianjia Sun , Rui Wang , Tiejun Dai
CPC classification number: H04N13/254 , G01S7/4816 , G01S7/4863 , G01S7/4865 , G01S7/497 , G01S17/89 , H01L27/14609 , H01L27/14627 , H01L27/14634 , H04N5/374 , H04N13/211 , H04N2013/0081
Abstract: A time of flight sensor includes control circuitry and a time of flight pixel array. The control circuitry is coupled to synchronously send a sync signal. The time of flight pixel array includes a plurality of time of flight pixel cells. Each one of the time of flight pixel cells includes a photosensor and a delay circuit. The photosensor is configured to generate an image signal in response to receiving photons from a light pulse reflected from an object. The delay circuit is coupled to generate a delayed sync signal in response to the sync signal. The delay circuit includes a delay transistor. The time of flight pixel array includes a transistor gradient where a transistor gate length of the delay transistor varies so that each of the time of flight pixel cells receive their respective delayed sync signal at a same time.
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公开(公告)号：US09819890B2
公开(公告)日：2017-11-14
申请号：US14828404
申请日：2015-08-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Le Huang , Tianjia Sun , Tiejun Dai
Abstract: Techniques and mechanisms to mitigate fixed pattern noise in image sensor data. In an embodiment, readout circuitry includes an adaptive analog-to-digital converter (ADC) comprising a differential amplifier and a feedback path coupled across the differential amplifier, where the ADC is to receive a ramp signal, a control signal associated with a transition rate of the ramp signal, and an analog signal generated by one or more pixels. In another embodiment, the feedback path and/or one or more other circuit elements coupled to the differential amplifier are configured, based on the control signal, to provide one of multiple loop gains with the differential amplifier. The ADC provides a digital output to determine a comparison based on the ramp signal and the analog signal.
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公开(公告)号：US20160061941A1
公开(公告)日：2016-03-03
申请号：US14473803
申请日：2014-08-29
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Jian Guo , Rui Wang , Tiejun Dai
Abstract: A time of flight imaging system includes a light source coupled to emit light pulses to an object in response a light source modulation signal generated in response to a reference modulation signal. Each pixel cell of a time of flight pixel cell array is coupled to sense light pulses reflected from the object in response a pixel modulation signal. A programmable pixel delay line circuit is coupled to generate the pixel modulation signal with a variable pixel delay programmed in response to a pixel programming signal. A control circuit is coupled to receive pixel information from the time of flight pixel array representative of the sensed reflected light pulses. The control circuit is coupled to vary the pixel programming signal during a calibration mode to synchronize the light pulses emitted from the light source with the pulses of the pixel modulation signal.
Abstract translation: 飞行时间成像系统包括耦合以响应于参考调制信号而产生的光源调制信号而向对象发射光脉冲的光源。 飞行时间像素单元阵列的每个像素单元耦合以响应于像素调制信号来感测从物体反射的光脉冲。 耦合可编程像素延迟线电路以响应于像素编程信号编程的可变像素延迟来产生像素调制信号。 控制电路被耦合以从代表所感测的反射光脉冲的飞行时间像素阵列接收像素信息。 控制电路被耦合以在校准模式期间改变像素编程信号，以使从光源发射的光脉冲与像素调制信号的脉冲同步。
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14.发明申请公开(公告)号：US20150288902A1
公开(公告)日：2015-10-08
申请号：US14247855
申请日：2014-04-08
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Tianjia Sun , Rui Wang , Liping Deng , Tiejun Dai
CPC classification number: H04N5/3698 , H04N5/357 , H04N5/378
Abstract: An image sensor read out circuit includes a first current mirror circuit in which a second current conducted through a second current path is controlled in response to a first current conducted through the first current path. The second current is conducted through an amplifier transistor of a pixel circuit. A first current source coupled to the first current path to provide a substantially constant current component of the first current. A second current source coupled to a power supply rail of the pixel circuit and coupled to the first current path to provide a ripple current component of the first current. The ripple current component provided by the second current source is responsive to a ripple in the power supply rail. The first current is responsive to a sum of the currents from the first and second current sources.
Abstract translation: 图像传感器读出电路包括第一电流镜电路，其中响应于通过第一电流路径传导的第一电流来控制通过第二电流路径传导的第二电流。 第二电流通过像素电路的放大器晶体管导通。 耦合到第一电流路径以提供第一电流的基本上恒定的电流分量的第一电流源。 耦合到所述像素电路的电源轨并耦合到所述第一电流路径以提供所述第一电流的纹波电流分量的第二电流源。 由第二电流源提供的纹波电流分量响应于电源轨道中的纹波。 第一电流响应于来自第一和第二电流源的电流的总和。
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公开(公告)号：US12249999B2
公开(公告)日：2025-03-11
申请号：US18171211
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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Patent Agency Ranking
公开(公告)号：US20240405039A1
公开(公告)日：2024-12-05
申请号：US18204261
申请日：2023-05-31
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Yaxin Zheng , Takayuki Goto , Rui Wang , Kazufumi Watanabe
IPC: H01L27/146
Abstract: An image sensor comprising a semiconductor substrate, a first source region, a second source region, and a shared gate electrode is described. The semiconductor substrate includes a first side and a second side opposite the first side. The first source region and the second source region are each disposed within the semiconductor substrate proximate to the first side. The first source region is separated from the second source region by an isolation structure disposed within the semiconductor substrate between the first source region and the second source region. The shared gate electrode is disposed proximate to the first side of the semiconductor substrate and coupled to the first source region and the second source region to respectively form a first transistor and a second transistor.
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公开(公告)号：US20240397223A1
公开(公告)日：2024-11-28
申请号：US18322421
申请日：2023-05-23
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang
IPC: H04N25/704 , H04N23/67 , H04N25/75
Abstract: An arithmetic logic unit includes a GC to binary stage, an adder stage, an adder output stage, an adder input latch stage coupled to latch outputs of the GC to binary stage, a feedback multiplexer stage coupled to receive the outputs of the GC to binary stage, a latch output multiplexer coupled to receive outputs of the first adder input latches, where the latch output multiplexer is configured to multiply the outputs of the first adder input latches by either −1 or −2, and an adder input multiplexer stage, where first inputs of the adder input multiplexer stage are coupled to receive outputs of the latch output multiplexer and second inputs of the adder input multiplexer stage are coupled to receive outputs of the second adder input latches. The arithmetic logic performs adaptive correlated multiple sampling for image sensing pixels and phase detection auto focus for other pixels.
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公开(公告)号：US12114092B2
公开(公告)日：2024-10-08
申请号：US18171227
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
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19.发明授权公开(公告)号：US12075179B2
公开(公告)日：2024-08-27
申请号：US18047588
申请日：2022-10-18
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang
IPC: H04N25/772 , G06F7/501 , G06F7/57
CPC classification number: H04N25/772 , G06F7/501 , G06F7/57
Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a signal latch stage coupled to a Gray code (GC) to binary stage. First inputs of an adder stage are coupled to receive outputs of the GC to binary stage. An adder input latch stage includes first and second adder input latches including first and second inputs coupled to receive outputs of the GC to binary stage. An adder input multiplexer stage includes an output coupled to second inputs of the adder stage, and first and second inputs coupled to outputs the first and second adder input latches, respectively.
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公开(公告)号：US20240283460A1
公开(公告)日：2024-08-22
申请号：US18171211
申请日：2023-02-17
Applicant: OMNIVISION TECHNOLOGIES, INC.
Inventor： Rui Wang , Hiroaki Ebihara
Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
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