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公开(公告)号：US10418535B2
公开(公告)日：2019-09-17
申请号：US15741876
申请日：2016-07-28
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Korbinian Perzlmaier , Anna Kasprzak-Zablocka , Christine Rafael , Christian Leirer
Abstract: An optoelectronic component includes a boundary layer is arranged between a semiconductor body and a metallic layer in a lateral direction, adjoins the semiconductor body at least in places, covers an active layer laterally, and has a lower refractive index compared to the semiconductor body, a metallic layer is configured to prevent the electromagnetic radiation generated during operation of the component and passes through the boundary layer from impinging on a mold body, the boundary layer is formed from a radiation-transmitting dielectric material having a refractive index of 1 to 2, and a layer thickness of the boundary layer is at least 400 nm and selected such that an amplitude of an evanescent wave, which is obtained in the event of total internal reflection at an interface between the boundary layer and the semiconductor body, is reduced to less than 37% of its original value within the boundary layer.
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公开(公告)号：US20180198045A1
公开(公告)日：2018-07-12
申请号：US15741876
申请日：2016-07-28
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Korbinian Perzlmaier , Anna Kasprzak-Zablocka , Christine Rafael , Christian Leirer
CPC classification number: H01L33/60 , H01L33/22 , H01L33/38 , H01L33/46 , H01L33/54 , H01L2933/0025 , H01L2933/005 , H01L2933/0058
Abstract: An optoelectronic component includes a boundary layer is arranged between a semiconductor body and a metallic layer in a lateral direction, adjoins the semiconductor body at least in places, covers an active layer laterally, and has a lower refractive index compared to the semiconductor body, a metallic layer is configured to prevent the electromagnetic radiation generated during operation of the component and passes through the boundary layer from impinging on a mold body, the boundary layer is formed from a radiation-transmitting dielectric material having a refractive index of 1 to 2, and a layer thickness of the boundary layer is at least 400 nm and selected such that an amplitude of an evanescent wave, which is obtained in the event of total internal reflection at an interface between the boundary layer and the semiconductor body, is reduced to less than 37% of its original value within the boundary layer.
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13.发明申请公开(公告)号：US20180013043A1
公开(公告)日：2018-01-11
申请号：US15544288
申请日：2016-01-11
Applicant: OSRAM Opto Semiconductors GmbH
IPC: H01L33/62 , H01L31/02 , H01L31/0203 , H01L33/48
CPC classification number: H01L33/62 , H01L31/02005 , H01L31/0203 , H01L33/40 , H01L33/486 , H01L2933/0066
Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip; and an electrical connection point that contacts the optoelectronic semiconductor chip, wherein the electrical connection point covers the optoelectronic semiconductor chip on the bottom thereof at least in some areas, the electrical connection point includes a contact layer facing toward the optoelectronic semiconductor chip, the electrical connection point includes at least one barrier layer arranged on a side of the contact layer facing away from the optoelectronic semiconductor chip, the electrical connection point includes a protective layer arranged on the side of the at least one barrier layer facing away from the contact layer, the layers of the electrical connection point are arranged one on top of another along a stack direction, and the stack direction runs perpendicular to a main extension plane of the optoelectronic semiconductor chip.
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公开(公告)号：US11195981B2
公开(公告)日：2021-12-07
申请号：US16607226
申请日：2018-05-08
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Isabel Otto , Anna Kasprzak-Zablocka , Christian Leirer
Abstract: A method of manufacturing semiconductor device includes providing a radiation emitting semiconductor chip having a first main surface, applying a metallic seed layer to a second main surface opposite the first main surface, galvanically depositing first and second metallic volume regions on the seed layer, depositing an adhesion promoting layer on the volume regions, and applying a casting compound at least between contact points, wherein before the metallic volume regions are galvanically deposited, a dielectric layer is first applied to the seed layer over its entire surface and openings are produced in the dielectric layer by etching, and a material of the metallic volume regions is deposited through the openings of the dielectric layer, wherein the dielectric layer is underetched at boundaries to the openings and the underetches are filled with material of the metallic volume regions during the galvanical depositing of the metallic volume regions.
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Patent Agency Ranking
公开(公告)号：US10424565B2
公开(公告)日：2019-09-24
申请号：US15303436
申请日：2015-03-18
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Andreas Weimar , Frank Singer , Anna Kasprzak-Zablocka , Sabine vom Dorp
Abstract: A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions.
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公开(公告)号：US10236419B2
公开(公告)日：2019-03-19
申请号：US15758186
申请日：2016-10-06
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Lutz Hoeppel , Korbinian Perzlmaier , Christine Rafael , Anna Kasprzak-Zablocka
Abstract: A component includes a semiconductor body, a carrier, and a stabilization layer arranged between the semiconductor body and the carrier in the vertical direction. The semiconductor body has a first semiconductor layer facing away from the carrier, a second semiconductor layer facing the carrier, and an active layer arranged between the first semiconductor layer and the second semiconductor layer. The carrier has a first via and a second via laterally spaced apart from the first via by means of an intermediate region. The first via is connected to the first semiconductor layer in an electrically conductive manner and the second via is connected to the second semiconductor layer in an electrically conductive manner. The stabilization layer is continuous, overlaps with the vias in a top view, and laterally bridges the intermediate region. The stabilization layer is electrically insulated from the vias and from the semiconductor body.
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公开(公告)号：US20180248083A1
公开(公告)日：2018-08-30
申请号：US15758186
申请日：2016-10-06
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Lutz Hoeppel , Korbinian Perzlmaier , Christine Rafael , Anna Kasprzak-Zablocka
CPC classification number: H01L33/486 , H01L33/382 , H01L33/54 , H01L33/60 , H01L33/62 , H01L2933/0033 , H01L2933/005 , H01L2933/0058 , H01L2933/0066
Abstract: A component includes a semiconductor body, a carrier, and a stabilization layer arranged between the semiconductor body and the carrier in the vertical direction. The semiconductor body has a first semiconductor layer facing away from the carrier, a second semiconductor layer facing the carrier, and an active layer arranged between the first semiconductor layer and the second semiconductor layer. The carrier has a first via and a second via laterally spaced apart from the first via by means of an intermediate region. The first via is connected to the first semiconductor layer in an electrically conductive manner and the second via is connected to the second semiconductor layer in an electrically conductive manner. The stabilization layer is continuous, overlaps with the vias in a top view, and laterally bridges the intermediate region. The stabilization layer is electrically insulated from the vias and from the semiconductor body.
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18.发明授权公开(公告)号：US09722136B2
公开(公告)日：2017-08-01
申请号：US15098926
申请日：2016-04-14
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Karl Engl , Markus Maute , Stefanie Rammelsberger , Anna Kasprzak-Zablocka
CPC classification number: H01L33/0075 , H01L33/382 , H01L33/385 , H01L33/405 , H01L33/52 , H01L2933/005
Abstract: An optoelectronic semiconductor chip has a semiconductor body and a substrate on which the semiconductor body is disposed. The semiconductor body has an active region disposed between a first semiconductor layer of a first conductor type and a second semiconductor layer of a second conductor type. The first semiconductor layer is disposed on the side of the active region facing the substrate. The first semiconductor layer is electrically conductively connected to a first termination layer that is disposed between the substrate and the semiconductor body. An encapsulation layer is disposed between the first termination layer and the substrate and, in plan view of the semiconductor chip, projects at least in some regions over a side face which delimits the semiconductor body.
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19.发明申请Semiconductor Chip, Optoelectronic Device with a Semiconductor Chip, and Method for Producing a Semiconductor Chip 有权具有半导体芯片的半导体芯片，光电子器件以及用于制造半导体芯片的方法公开(公告)号：US20170033092A1
公开(公告)日：2017-02-02
申请号：US15303436
申请日：2015-03-18
Applicant: OSRAM Opto Semiconductors GmbH
Inventor： Andreas Weimar , Frank Singer , Anna Kasprzak-Zablocka , Sabine vom Dorp
Abstract: A semiconductor chip, an optoelectronic device including a semiconductor chip, and a method for producing a semiconductor chip are disclosed. In an embodiment the chip includes a semiconductor body with a first main surface and a second main surface arranged opposite to the first main surface, wherein the semiconductor body includes a p-doped sub-region, which forms part of the first main surface, and an n-doped sub-region, which forms part of the second main surface and a metallic contact element that extends from the first main surface to the second main surface and that is electrically isolated from one of the sub-regions.
Abstract translation: 公开了半导体芯片，包括半导体芯片的光电子器件和半导体芯片的制造方法。 在一个实施例中，芯片包括具有第一主表面和与第一主表面相对布置的第二主表面的半导体本体，其中半导体主体包括形成第一主表面的一部分的p掺杂子区域，以及 形成第二主表面的一部分的n掺杂子区域和从第一主表面延伸到第二主表面并且与一个子区域电隔离的金属接触元件。
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