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    Low power receiver with wide input voltage range
    11.
    发明授权
    Low power receiver with wide input voltage range 有权
    低功率接收器，输入电压范围宽

    公开(公告)号：US09536593B1

    公开(公告)日：2017-01-03

    申请号：US15162430

    申请日：2016-05-23

    Applicant: QUALCOMM Incorporated

    Inventor： LuVerne Ray Peterson ,  Thomas Bryan ,  Jacob Schneider

    IPC: G11C11/4093 ,  H03F3/50 ,  G11C7/10 ,  H03K19/003

    CPC classification number: G11C11/4093 ,  G11C7/1078 ,  G11C7/1084 ,  H03F3/505 ,  H03F2200/69 ,  H03K19/00315 ,  H03K19/018521

    Abstract: An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower transistor configured to pass a threshold-voltage-reduced version of the input signal while the first binary state of the input signal equals a high voltage greater than the low voltage.

    Abstract translation: 输入接收器设置有传输晶体管，其被控制以仅在输入信号的第一二进制状态等于低电压时将输入信号传递到反相器。 输入接收器还包括源极跟随器晶体管，其被配置为在输入信号的第一二进制状态等于大于低电压的高电压时传递输入信号的阈值电压降低版本。

    SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST
    12.
    发明申请
    SYSTEMS AND METHODS FOR WAFER-LEVEL LOOPBACK TEST 有权
    用于水平回波测试的系统和方法

    公开(公告)号：US20160025807A1

    公开(公告)日：2016-01-28

    申请号：US14339224

    申请日：2014-07-23

    Applicant: QUALCOMM Incorporated

    Inventor： Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  Reza Jalilizeinali ,  Tin Tin Wee ,  Stephen Robert Knol ,  LuVerne Ray Peterson

    IPC: G01R31/3177

    CPC classification number: G01R31/3177 ,  G01R31/31716 ,  G01R31/318513

    Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

    Abstract translation: 提供了用于环回测试的电路和方法。 一个管芯将每个发射器（TX）的接收器（RX）以及每个接收器的TX都包含在内。 该架构被应用于每个位，因此，例如，在操作期间发送或接收32个数据位的管芯将具有32个收发器（每个位一个）。 专注于收发器之一，环回架构包括TX数据路径和RX数据路径，其通过诸如收发器之间的通孔的外部接点相互耦合。 芯片还包括馈送TX数据路径的发射时钟树和馈送RX数据路径的接收时钟树。 传输时钟树通过露出在芯片表面上的导电时钟节点馈送接收时钟树。 一些系统还包括时钟路径中的可变延迟。

    DRIVER USING PULL-UP NMOS TRANSISTOR
    16.
    发明申请
    DRIVER USING PULL-UP NMOS TRANSISTOR 审中-公开
    驱动器使用拉高NMOS晶体管

    公开(公告)号：US20160285453A1

    公开(公告)日：2016-09-29

    申请号：US14957188

    申请日：2015-12-02

    Applicant: QUALCOMM Incorporated

    Inventor： Stephen Clifford Thilenius ,  Patrick Isakanian ,  Alvin Leng Sun Loke ,  Thomas Clark Bryan ,  LuVerne Ray Peterson

    IPC: H03K19/0175 ,  H03K5/14

    CPC classification number: H03K19/017518 ,  G11C7/1057 ,  H03K5/14 ,  H03K19/018507

    Abstract: In one embodiment, a system comprises a pre-driver circuit and a driver. The pre-driver circuit is powered by a first supply voltage, and configured to output a pre-drive signal. The driver comprises a pull-up NMOS transistor having a drain coupled to a second supply voltage, and a source coupled to an output of the driver, wherein the second supply voltage is lower than the first supply voltage by at least a threshold voltage of the pull-up NMOS transistor. The driver also comprises a drive circuit coupled to a gate of the pull-up NMOS transistor, wherein the drive circuit is configured to receive the pre-drive signal and to drive the gate of the pull-up NMOS transistor with a voltage approximately equal to the first supply voltage to drive the output of the driver to a high state depending on a logic state of the pre-drive signal.

    Abstract translation: 在一个实施例中，系统包括预驱动器电路和驱动器。 预驱动器电路由第一电源电压供电，并且被配置为输出预驱动信号。 驱动器包括具有耦合到第二电源电压的漏极的上拉NMOS晶体管和耦合到驱动器的输出的源，其中第二电源电压低于第一电源电压至少一个阈值电压 上拉式NMOS晶体管。 驱动器还包括耦合到上拉NMOS晶体管的栅极的驱动电路，其中驱动电路被配置为接收预驱动信号并且驱动上拉NMOS晶体管的栅极，其电压近似等于 根据预驱动信号的逻辑状态，第一电源电压将驱动器的输出驱动到高电平状态。

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