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公开(公告)号：US09654090B2
公开(公告)日：2017-05-16
申请号：US15138142
申请日：2016-04-25
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K3/00 , H03K5/15 , H01L23/538 , G06F1/10 , G11C7/22 , H01L25/065
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
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公开(公告)号：US09614703B2
公开(公告)日：2017-04-04
申请号：US14852088
申请日：2015-09-11
Applicant: QUALCOMM Incorporated
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , LuVerne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.
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公开(公告)号：US20160308519A1
公开(公告)日：2016-10-20
申请号：US15138142
申请日：2016-04-25
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K5/15 , H01L23/538 , H01L25/065
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
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公开(公告)号：US20160294585A1
公开(公告)日：2016-10-06
申请号：US14852088
申请日：2015-09-11
Applicant: QUALCOMM Incorporated
Inventor： Mohammed Mizanur Rahman , Thomas Clark Bryan , Jacob Stephen Schneider , LuVerne Ray Peterson , Tin Tin Wee , Alvin Leng Sun Loke
CPC classification number: H04L25/03885 , H04B1/16 , H04L25/0278 , H04L25/029 , H04L25/0292 , H04L25/0298 , H04L25/03 , H04L25/03834 , H04L25/03878 , H04L25/08
Abstract: Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but-for the equalizer.
Abstract translation: 公开了使用不匹配阻抗和均衡器来提供接收和捕获数据以节省功率的方法，系统和电路。 一种与传输线通信的数据接收机，所述数据接收机具有相对于所述传输线的特性阻抗失配的终端阻抗; 以及与数据接收器通信的均衡器，均衡器被配置为从数据接收器接收信道发送的数据信号并且重新形成信号以减小失真RC衰减; 其中所述电路被配置为以第一模式可选择地操作，其中终端阻抗相对于传输线的特性阻抗匹配，以及第二模式，其中终端阻抗相对于传输线的特性阻抗失配， 信号是不可恢复的，但是对于均衡器。
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公开(公告)号：US10044342B2
公开(公告)日：2018-08-07
申请号：US15178389
申请日：2016-06-09
Applicant: QUALCOMM Incorporated
Inventor： LuVerne Ray Peterson , Thomas Bryan , Tin Tin Wee
IPC: H03K3/012 , H03K5/134 , H03K3/356 , H03K19/00 , H04L25/03 , G06F1/32 , H03K17/16 , H03K19/003 , H03K5/00
Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.
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Patent Agency Ranking
公开(公告)号：US20160294383A1
公开(公告)日：2016-10-06
申请号：US14792441
申请日：2015-07-06
Applicant: QUALCOMM, Incorporated
Inventor： Mohammed Mizanur Rahman , Jacob Stephen Schneider , Thomas Clark Bryan , LuVerne Ray Peterson , Gregory Francis Lynch , Alvin Leng Sun Loke
IPC: H03K17/687
CPC classification number: H03K17/687 , H03F3/45197 , H03F2203/45488 , H03F2203/45494 , H03F2203/45504 , H04L25/0272 , H04L25/0292 , H04L25/03878
Abstract: A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.
Abstract translation: 提供了可编程均衡器和相关方法。 均衡器包括分别与第一电压轨（Vdd）和第二电压轨（地）之间的一对输入FET和一对负载电阻串联耦合的一对电流设定场效应晶体管（FET）。 可编程均衡电路耦合在输入FET的源极之间，包括多个可选择的电阻路径和可变电容器，其也可以被配置为多个可选择的电容路径。 每个可选择的电阻路径（以及每个可选择的电容路径）包括用于选择性地耦合在输入FET的源极之间的对应的电阻（或电容）路径的选择FET。 在其中一个输入FET被参考栅极电压偏置的情况下，每个选择FET的源极耦合到这种输入FET的源极。
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公开(公告)号：US09350339B2
公开(公告)日：2016-05-24
申请号：US14335681
申请日：2014-07-18
Applicant: QUALCOMM Incorporated
Inventor： Thomas Clark Bryan , Alvin Leng Sun Loke , Stephen Knol , Gregory Francis Lynch , Tin Tin Wee , LuVerne Ray Peterson , Yue Li
IPC: H03K3/00 , H03K5/15 , H01L23/538 , G06F1/10 , G11C7/22 , H01L25/065
CPC classification number: H03K5/15013 , G06F1/10 , G11C7/22 , H01L23/5384 , H01L23/5389 , H01L25/0655 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/20 , H01L2224/24137 , H01L2224/73267 , H01L2924/15311
Abstract: Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.
Abstract translation: 提供了芯片到芯片时钟分配的电路。 系统包括第一管芯上的传输时钟树和第二管芯上的接收时钟树。 发送时钟树和接收时钟树是相同的或非常接近相同的，所以发送时钟树上的给定位的插入延迟与对应于给定位的位的插入延迟相同 接收时钟树。 虽然在同一个时钟树中可能存在从位到位的时钟偏差，但是不同芯片上的相应位具有相同的时钟插入延迟。
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8.发明授权公开(公告)号：US09245870B1
公开(公告)日：2016-01-26
申请号：US14516763
申请日：2014-10-17
Applicant: QUALCOMM Incorporated
Inventor： LuVerne Ray Peterson , Thomas Clark Bryan , Alvin Leng Sun Loke , Tin Tin Wee , Gregory Francis Lynch , Stephen Robert Knol
IPC: H01L25/00 , H01L25/065
CPC classification number: H01L25/065 , G06F1/10 , G06F17/5072 , G06F2217/62 , G06F2217/78 , H01L2924/0002 , H04L7/0095 , H01L2924/00
Abstract: A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.
Abstract translation: 电路包括具有暴露的数据节点的第一阵列的第一管芯和具有暴露的数据节点的第二阵列的第二管芯，其中第一阵列的给定数据节点对应于第二阵列上的相应的数据节点，此外， 所述第一阵列和所述第二阵列共享所述数据节点的空间布置，其中所述第一裸片具有用于所述第一阵列的第一侧上的所述第一阵列的每个数据节点的数据输入和顺序逻辑电路，并且其中所述第二阵列 管芯具有用于第二阵列的第二侧上的第二阵列的每个数据节点的数据输出和顺序逻辑电路，第一和第二侧是不同的。
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公开(公告)号：US09977078B2
公开(公告)日：2018-05-22
申请号：US14339224
申请日：2014-07-23
Applicant: QUALCOMM Incorporated
Inventor： Alvin Leng Sun Loke , Thomas Clark Bryan , Reza Jalilizeinali , Tin Tin Wee , Stephen Robert Knol , LuVerne Ray Peterson
IPC: G06F17/50 , G01R31/3177 , G01R31/3185 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31716 , G01R31/318513
Abstract: Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.
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公开(公告)号：US20170359053A1
公开(公告)日：2017-12-14
申请号：US15178389
申请日：2016-06-09
Applicant: QUALCOMM Incorporated
Inventor： LuVerne Ray Peterson , Thomas Bryan , Tin Tin Wee
CPC classification number: H03K3/012 , G06F1/32 , H03K3/356113 , H03K5/134 , H03K17/161 , H03K19/0005 , H03K19/0008 , H03K19/0013 , H03K19/00361 , H03K2005/00195 , H04L25/03019
Abstract: A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.
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