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    FINE PITCH AND SPACING INTERCONNECTS WITH RESERVE INTERCONNECT PORTION
    12.
    发明申请
    FINE PITCH AND SPACING INTERCONNECTS WITH RESERVE INTERCONNECT PORTION 审中-公开

    公开(公告)号：US20190067178A1

    公开(公告)日：2019-02-28

    申请号：US15690541

    申请日：2017-08-30

    Applicant: QUALCOMM Incorporated

    Inventor： Kuiwon Kang ,  Houssam Jomaa ,  Layal Rouhana

    IPC: H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L21/768

    Abstract: Some features pertain to a substrate that includes a first dielectric, a first interconnect, and a second interconnect. The first interconnect is at least partially embedded in the first dielectric layer. The first interconnect includes a first portion and a second portion. The first portion is configured to increase reliability as compared to a substrate having only a second portion of a first interconnect. The increase in reliability due at least in part to the first portion providing additional interconnect material to mitigate interconnect material lost through electromigration. A part of the second portion (of the first interconnect) is free of the first dielectric and may be configured to be coupled to another device.

    INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS
    16.
    发明申请
    INTEGRATED CIRCUIT (IC) PACKAGE SUBSTRATE WITH EMBEDDED TRACE SUBSTRATE (ETS) LAYER ON A SUBSTRATE, AND RELATED FABRICATION METHODS 有权

    公开(公告)号：US20220068780A1

    公开(公告)日：2022-03-03

    申请号：US17405494

    申请日：2021-08-18

    Applicant: QUALCOMM Incorporated

    Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Joonsuk Park

    IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

    Abstract: Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (μm)/5.0 μm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.

    Substrate comprising recessed interconnects and a surface mounted passive component
    17.
    发明授权
    Substrate comprising recessed interconnects and a surface mounted passive component 有权

    公开(公告)号：US11075260B2

    公开(公告)日：2021-07-27

    申请号：US16176915

    申请日：2018-10-31

    Applicant: QUALCOMM Incorporated

    Inventor： Kuiwon Kang ,  Chin-Kwan Kim ,  Hong Bok We ,  Jaehyun Yeon

    IPC: H01L23/498 ,  H01L49/02 ,  H01L21/56 ,  H01L23/31

    Abstract: A device that includes a substrate, a die, and a discrete capacitor. The substrate includes a dielectric layer and a plurality of interconnects formed in the dielectric layer. The discrete capacitor is coupled to the substrate through a first solder interconnect and a second solder interconnect. The first solder interconnect and the second solder interconnect are located within the dielectric layer. The die is coupled to the substrate. In some implementations, the first solder interconnect is located in a first cavity of the dielectric layer, and the second solder interconnect is located in a second cavity of the dielectric layer. In some implementations, the substrate includes a first cavity that is filled with a first via and the first solder interconnect; and a second cavity that is filled with a second via and the second solder interconnect.

    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES
    19.
    发明申请
    PACKAGE SUBSTRATE WITH TESTING PADS ON FINE PITCH TRACES 有权
    包装衬底，带有测试垫

    公开(公告)号：US20140247573A1

    公开(公告)日：2014-09-04

    申请号：US13783168

    申请日：2013-03-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： Chin-Kwan Kim ,  Kuiwon Kang ,  Omar J. Bchir

    IPC: H05K1/11 ,  H05K3/22 ,  H05K3/30

    CPC classification number: H05K1/111 ,  G01R31/2818 ,  H05K1/0268 ,  H05K3/3452 ,  H05K2201/10674 ,  Y10T29/49004 ,  Y10T29/49124 ,  Y10T29/4913

    Abstract: Some implementations provide a substrate that includes several traces, a solder resist layer covering the several traces, and a testing pad coupled to a trace from the several traces. The testing pad is at least partially exposed and at least partially free of the solder resist layer when a chip is coupled to the substrate. In some implementations, the several traces have a pitch that is 100 microns (nm) or less. In some implementations, the substrate is a package substrate. In some implementations, the package substrate is a package substrate on which a thermal compression flip chip is mounted during an assembly process. In some implementations, the testing pad is free of a direct connection with a bonding component of the chip when the chip is coupled to the substrate. In some implementations, the bonding component is one of a solder ball.

    Abstract translation: 一些实施方案提供了包括几条迹线的衬底，覆盖几条迹线的阻焊层，以及耦合到几条迹线的迹线的测试焊盘。 当芯片耦合到衬底时，测试焊盘至少部分地暴露并且至少部分地不含阻焊层。 在一些实施方案中，几条迹线具有100微米（nm）或更小的间距。 在一些实施方式中，衬底是封装衬底。 在一些实施方案中，封装衬底是在组装过程期间安装热压缩倒装芯片的封装衬底。 在一些实施方案中，当芯片耦合到衬底时，测试焊盘不与芯片的焊接部件直接连接。 在一些实施方式中，接合部件是焊球之一。

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