公开(公告)号：US20150054567A1

公开(公告)日：2015-02-26

申请号：US13975074

申请日：2013-08-23

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

Abstract translation: 互连电平上的第一互连将CMOS器件的PMOS漏极的第一子集连接在一起。 互连层上的第二互连将PMOS排水沟的第二子集连接在一起。 PMOS漏极的第二子集不同于PMOS漏极的第一子集。 第一互连和第二互连在互连级别上断开连接。 互连电平上的第三互连将CMOS器件的NMOS漏极的第一子集连接在一起。 互连电平上的第四互连将NMOS漏极的第二子集连接在一起。 NMOS漏极的第二子集与NMOS漏极的第一子集不同。 第三互连和第四互连在互连级别上断开。 第一，第二，第三和第四互连通过至少一个其它互连级连接在一起。

公开(公告)号：US20200168604A1

公开(公告)日：2020-05-28

申请号：US16777639

申请日：2020-01-30

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482 ,  H01L23/528

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

公开(公告)号：US20200152630A1

公开(公告)日：2020-05-14

申请号：US16744227

申请日：2020-01-16

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi RASOULI ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H01L23/535 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238 ,  H01L27/02 ,  H01L23/482

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together through at least one other interconnect level.

公开(公告)号：US20160343661A1

公开(公告)日：2016-11-24

申请号：US15159744

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Stanley Seungchul SONG ,  Kern RIM ,  John Jianhong ZHU

IPC: H01L23/535 ,  H01L27/092 ,  H01L29/45 ,  H01L27/02

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L27/0207

Abstract: A MOS device includes a first interconnect extending in a first direction, the first interconnect being configured in a metal layer. The MOS device further includes a second interconnect extending in the first direction parallel to the first interconnect, the second interconnect being configured in the metal layer. The MOS device further includes a gate interconnect extending in a second direction orthogonal to the first direction, the gate interconnect being situated in a first layer below the metal layer, wherein the gate interconnect is coupled to the first interconnect by a first via. The MOS device further includes a third interconnect extending in the second direction, the third interconnect being coupled to both the first and second interconnects, wherein the third interconnect is coupled to the first interconnect by a second via, and wherein the second via contacts the first via.

Abstract translation: MOS器件包括沿第一方向延伸的第一互连，第一互连配置在金属层中。 MOS器件还包括在第一方向上平行于第一互连延伸的第二互连，第二互连配置在金属层中。 MOS器件还包括在与第一方向正交的第二方向上延伸的栅极互连，栅极互连位于金属层下方的第一层中，其中栅极互连通过第一通孔耦合到第一互连。 MOS器件还包括在第二方向上延伸的第三互连，第三互连件耦合到第一和第二互连件，其中第三互连通过第二通孔耦合到第一互连，并且其中第二通孔接触第一互连 通过。

公开(公告)号：US20150302129A1

公开(公告)日：2015-10-22

申请号：US14255677

申请日：2014-04-17

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Mukul GUPTA ,  Ohsang KWON ,  Foua VANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/70466

Abstract: In an embodiment, a method in the manufacture of triple-patterning lithography masks, each mask represented by one of three colors, where each cell layout has exactly one polygonal pattern at one-half the different-color spacing from its left boundary, and exactly one polygonal pattern at one-half the different-color spacing from its right boundary. During placement of the cell layouts into a row, the method includes switching assigned colors in a cell layout to ensure that no two polygonal patterns of the same color in the layout are at a distance from each other less than the same-color spacing.

Abstract translation: 在一个实施例中，制造三重图案化光刻掩模的方法，每个掩模由三种颜色之一表示，其中每个单元布局具有与其左边界不同的颜色间隔的一半的正好一个多边形图案，并且精确地 一个多边形图案与其右边界的不同颜色间距的一半。 在将单元格布局放置到行中的过程中，该方法包括切换单元格布局中分配的颜色，以确保布局中相同颜色的两个多边形图案彼此之间的距离小于相同颜色的间距。

公开(公告)号：US20150221639A1

公开(公告)日：2015-08-06

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Satyanarayana SAHU ,  Divya GANGADHARAN ,  Chih-lung KAO ,  Renukprasad Shreedhar HIREMATH ,  Animesh DATTA ,  Qi YE

IPC: H01L27/088 ,  G06F17/50 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压，并且在栅极的另一侧上的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。

公开(公告)号：US20150054568A1

公开(公告)日：2015-02-26

申请号：US13975185

申请日：2013-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi RASOULI ,  Michael Joseph BRUNOLLI ,  Christine Sung-An HAU-RIEGE ,  Mickael MALABRY ,  Sucheta Kumar HARISH ,  Prathiba BALASUBRAMANIAN ,  Kamesh MEDISETTI ,  Nikolay BOMSHTEIN ,  Animesh DATTA ,  Ohsang KWON

IPC: H01L27/092 ,  H03K17/687 ,  H03K17/16 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract translation: 具有多个PMOS晶体管的CMOS器件，每个具有PMOS漏极和多个NMOS晶体管，每个具有NMOS漏极包括在长度方向上延伸的互连级上的第一互连，以将PMOS漏极连接在一起。 互连级上的第二互连在长度方向上延伸以将NMOS漏极连接在一起。 在至少一个附加互连级上的一组互连将第一互连和第二互连耦合在一起。 互连层上的第三互连件垂直于长度方向延伸，并且从互连组中偏移以将第一互连和第二互连连接在一起。

公开(公告)号：US20150028495A1

公开(公告)日：2015-01-29

申请号：US14338229

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Esin TERZIOGLU ,  Hadi BUNNALIM

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥V2，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。