公开(公告)号：US20200210299A1

公开(公告)日：2020-07-02

申请号：US16815718

申请日：2020-03-11

Applicant: QUALCOMM Incorporated

Inventor： Rahul GULATI ,  Andrew Evan GRUBER ,  Brendon Lewis JOHNSON ,  Jay Chunsup YUN ,  Donghyun KIM ,  Alex Kwang Ho JONG ,  Anshuman SAXENA

IPC: G06F11/22 ,  G06T1/20 ,  G06T15/00 ,  G06F11/07 ,  G01R31/317 ,  G01R31/3187 ,  G06F11/277

Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.

公开(公告)号：US20180231609A1

公开(公告)日：2018-08-16

申请号：US15835227

申请日：2017-12-07

Applicant: QUALCOMM Incorporated

Inventor： Arvind JAIN ,  Nishi BHUSHAN SINGH ,  Rahul GULATI ,  Pranjal BHUYAN ,  Rakesh Kumar KINGER ,  Roberto AVERBUJ

IPC: G01R31/317 ,  G01R31/3187 ,  G01R31/3183 ,  G01R31/3185 ,  G01R31/319

Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.

公开(公告)号：US20240321096A1

公开(公告)日：2024-09-26

申请号：US18189050

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Ali Reza ABBASPOUR ,  Rahul GULATI ,  Ahmed Kamel SADEK

IPC: G08G1/13 ,  B60W50/14 ,  B60W60/00 ,  G08G1/017

CPC classification number: G08G1/13 ,  B60W50/14 ,  B60W60/0053 ,  G08G1/017 ,  B60W2050/143 ,  B60W2420/403 ,  B60W2420/408 ,  B60W2554/4041

Abstract: Systems and methodologies for determining validity of a location of a vehicle include obtaining a first location of the vehicle corresponding to a first time. A first RSU signal including an indication of a location of the first RSU is received at the vehicle from a first Roadside Unit (RSU). One or more location measurements are obtained of the vehicle relative thee first RSU based on one or more sensors of the vehicle. The first location of the vehicle is compared with the first RSU-based location of the vehicle.

公开(公告)号：US20240227825A1

公开(公告)日：2024-07-11

申请号：US18152222

申请日：2023-01-10

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Rahul GULATI

IPC: B60W50/02 ,  B60W50/00 ,  B60W50/035 ,  G07C5/08

CPC classification number: B60W50/0205 ,  B60W50/0098 ,  B60W50/035 ,  G07C5/085

Abstract: Aspects of the present disclosure provide techniques and apparatus for testing a mixed safety system, such as system included in a vehicle. An example method of operating a vehicle includes operating an electronic control unit (ECU) in a first state; detecting one or more criteria being satisfied to perform a test associated with the ECU; and performing the test associated with the ECU in response to detecting the one or more criteria being satisfied, while the ECU is in a second state different from the first state.

公开(公告)号：US20240067110A1

公开(公告)日：2024-02-29

申请号：US18457066

申请日：2023-08-28

Applicant: QUALCOMM Incorporated

Inventor： Amit ANEJA ,  Vasant Kumar EASWARAN ,  Rahul GULATI

IPC: B60R16/03 ,  B60R16/023

CPC classification number: B60R16/03 ,  B60R16/0232

Abstract: Techniques and apparatus for power supply monitoring in in-vehicle systems, such as advanced driver assistance systems (ADASs), in-vehicle infotainment (IVI) systems, and/or automated driving (AD) systems. One example method of power supply monitoring generally includes regulating power to a main domain of a system on a chip (SoC) using at least one main domain (MD) power management integrated circuit (PMIC); regulating power to a safety domain of the SoC using at least one safety domain (SD) PMIC; powering the at least one SD PMIC using a SD PMIC power supply rail; and monitoring the SD PMIC power supply rail using the at least one MD PMIC. For certain aspects, the method further includes powering the at least one MD PMIC using a MD PMIC power supply rail and monitoring the MD PMIC power supply rail using the at least one SD PMIC.

公开(公告)号：US20230203796A1

公开(公告)日：2023-06-29

申请号：US18181035

申请日：2023-03-09

Applicant: QUALCOMM Incorporated

Inventor： Kiran Kumar MALIPEDDI ,  Rahul GULATI

IPC: E03C1/046

CPC classification number: E03C1/0465

Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

公开(公告)号：US20220243437A1

公开(公告)日：2022-08-04

申请号：US17161731

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Kiran Kumar MALIPEDDI ,  Rahul GULATI

IPC: E03C1/046

Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.

公开(公告)号：US20220020340A1

公开(公告)日：2022-01-20

申请号：US17092165

申请日：2020-11-06

Applicant: QUALCOMM Incorporated

Inventor： Paul Christopher John WIERCIENSKI ,  John Chi Kit WONG ,  Rahul GULATI ,  Gary Arthur CIAMBELLA ,  Sreekanth MODAIKKAL

IPC: G09G5/37 ,  G06T1/20 ,  G06F21/64 ,  G06F16/23

Abstract: The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.

公开(公告)号：US20210234376A1

公开(公告)日：2021-07-29

申请号：US16774023

申请日：2020-01-28

Applicant: QUALCOMM Incorporated

Inventor： Palkesh JAIN ,  Rahul GULATI

IPC: H02J4/00 ,  G06F1/3203 ,  H01L23/525 ,  H02J9/00 ,  H01L27/08 ,  G06F1/18

Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

公开(公告)号：US20210064905A1

公开(公告)日：2021-03-04

申请号：US16554735

申请日：2019-08-29

Applicant: QUALCOMM Incorporated

Inventor： Rahul GULATI ,  Robert HARDACKER ,  Sumant PARANJPE ,  Reza KAKOEE ,  John Chi Kit WONG ,  Sanjay GUPTA ,  Alex JONG

IPC: G06K9/32 ,  G06T13/20 ,  G08B6/00 ,  G06F3/01 ,  G06F3/0481

Abstract: Certain aspects of the present disclosure generally relate to testing functionality of the display system. An example method generally includes selecting a first data integrity check value, associated with a region of interest (ROI) of an input frame, among a set of data integrity check values stored on a memory device, the data integrity check values are associated with an animation comprising a plurality of frames, and at least one of the frames of the animation corresponds to the input frame; processing, with a display processor, the input frame; calculating a second data integrity check value on the ROI of the input frame after the display processor processes the input frame; comparing, with a comparator, the data integrity check values; and generating, with the comparator, an interrupt if the comparison indicates that the values do not match.