公开(公告)号：US20150365226A1

公开(公告)日：2015-12-17

申请号：US14834219

申请日：2015-08-24

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Joseph Cheung

IPC: H04L7/027 ,  H04L25/14

CPC classification number: H04L7/027 ,  G06F13/4072 ,  G06F13/4295 ,  H04L25/00 ,  H04L25/14

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract translation: 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 数据比特序列被转换成M个转换号码，然后转换成符号序列。 通过N线接收符号序列。 可以有效地将时钟信号嵌入到符号序列的传输中。 符号序列中的每一个可以基于M个转移号码中的一个和符号序列中的前一个的值来选择。

公开(公告)号：US09172426B2

公开(公告)日：2015-10-27

申请号：US14199064

申请日：2014-03-06

Applicant: QUALCOMM Incorporated

Inventor： Chulkyu Lee ,  George Alan Wiley ,  Shoichiro Sengoku

IPC: H04B3/00 ,  H04L25/00 ,  H04B3/06 ,  G06F13/40

CPC classification number: H04B3/06 ,  G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within electronic equipment. Transmission lines are selectively terminated in an N-phase polarity encoded transmitter when the transmission lines would otherwise be undriven. Data is mapped to a sequence of symbols to be transmitted on a plurality of wires. The sequence of symbols is encoded in three signals. Each of the three terminals may be driven such that transistors are activated to couple a terminal to first and second voltage levels through a pair of impedances when the terminal would otherwise be undriven. The terminal is then pulled toward an intermediate voltage level while the terminal presents a desired impedance level to a transmission line.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 当传输线否则将被驱动时，传输线选择性地终止在N相极性编码的发射机中。 数据被映射到要在多根线上传输的符号序列。 符号序列被编码为三个信号。 可以驱动三个端子中的每一个，使得晶体管被激活以在端子否则将不被引导时通过一对阻抗将端子耦合到第一和第二电压电平。 然后将终端拉向中间电压电平，同时终端向传输线呈现期望的阻抗电平。

公开(公告)号：US20150248373A1

公开(公告)日：2015-09-03

申请号：US14634106

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/42 ,  G06F11/22 ,  G06F11/16 ,  G06F11/30

CPC classification number: G06F13/4291 ,  G06F11/1679 ,  G06F11/221 ,  G06F11/3027 ,  H03M13/096

Abstract: Various aspects directed towards facilitating an error detection optimization over a shared bus are disclosed. A master device is coupled to a slave device, and an encoded communication of a word is facilitated between the master device and the slave device via a control data bus. The encoded communication is encoded according to a protocol that allocates a plurality of least significant bits of the encoded communication to facilitate maximizing an error detection constant. The protocol allocates the plurality of least significant bits to include at least one additional error detection bit or at least a first most significant bit of a data portion of the word.

Abstract translation: 公开了涉及促进共享总线上的错误检测优化的各个方面。 主设备耦合到从设备，并且经由控制数据总线在主设备和从设备之间促进字的编码通信。 编码通信根据分配编码通信的多个最低有效位的协议进行编码，以便最大化错误检测常数。 协议分配多个最低有效位以包括字的数据部分的至少一个附加错误检测位或至少第一最高有效位。

公开(公告)号：US20150095537A1

公开(公告)日：2015-04-02

申请号：US14504413

申请日：2014-10-01

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: G06F13/362 ,  G06F1/32

CPC classification number: G06F13/362 ,  G06F1/3253 ,  G06F13/4295

Abstract: A device is provided comprising a control data bus including at least a first line. A master device may be coupled to the control data bus and configured to control the control data bus. A plurality of slave devices may be coupled to the control data bus and share the first line. The master device may be configured to send a single global wake up signal on the control data bus that causes any sleeping slave devices to wake up. Alternatively, the master device may send a global wake up signal followed by a targeted sleep signal to non-targeted slave devices to implement a “targeted wake up” of specific slave devices. The master device may send the single global wake up signal by bringing the first line low for a predetermined period of time.

Abstract translation: 提供了包括至少包括第一行的控制数据总线的设备。 主设备可以耦合到控制数据总线并且被配置为控制控制数据总线。 多个从设备可以耦合到控制数据总线并共享第一行。 主设备可以被配置为在控制数据总线上发送单个全局唤醒信号，使得任何休眠的从设备唤醒。 或者，主设备可以发送全局唤醒信号，然后将目标睡眠信号发送到非目标从设备，以实现特定从设备的“目标唤醒”。 主设备可以通过使第一行低一段预定时间来发送单个全局唤醒信号。

公开(公告)号：US20140348214A1

公开(公告)日：2014-11-27

申请号：US14459132

申请日：2014-08-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee

IPC: H04B1/7073

CPC classification number: H04L25/40 ,  H03L7/00 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14 ,  H04L25/493

Abstract: A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.

Abstract translation: 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。

公开(公告)号：US20140286466A1

公开(公告)日：2014-09-25

申请号：US14220056

申请日：2014-03-19

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  Joseph Cheung ,  George Alan Wiley

IPC: H04L7/04

CPC classification number: H04L7/0087 ,  H03K3/017 ,  H03K5/13 ,  H03K5/133 ,  H03K5/134 ,  H03K5/14 ,  H03K5/153 ,  H03K5/1534 ,  H03K19/00 ,  H03K2005/00293 ,  H03L7/081 ,  H04L7/0037 ,  H04L7/033 ,  H04L7/0331

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract translation: 描述了一种方法，装置和计算机程序产品。 该装置通过确定从多线开漏链路接收的信号中的转变来产生用于从多线开漏链路接收数据的接收时钟信号，响应于该转换产生时钟脉冲，延迟时钟脉冲 如果转换处于第一方向，则通过预先配置的第一间隔，并且如果转换处于第二方向，则将时钟延迟预先配置的第二间隔。 基于与通信接口相关联的上升时间和/或下降时间来配置预配置的第一和/或第二间隔，并且可以通过测量与为第一和第二校准转换产生的时钟脉冲相关联的相应延迟来校准预配置的第一和/或第二间隔。

公开(公告)号：US20140270005A1

公开(公告)日：2014-09-18

申请号：US14210246

申请日：2014-03-13

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L27/20

CPC classification number: H04L27/2071 ,  G06F13/4063 ,  G08C19/00 ,  H04B1/06 ,  H04B3/00 ,  H04L25/0272 ,  H04L25/0292 ,  H04L69/18

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract translation: 提供用于接收机设备的终端网络以支持D-PHY信令和N阶因子信令。 多个动态可配置开关中的每一个的第一端耦合到公共节点。 多个电阻中的每一个的第一端耦合到相应开关的第二端。 多个端子接收差分信号，并且每个端子耦合到电阻的对应的第二端。 多个差分接收器中的每一个耦合在终端网络的两个终端之间，其中第一差分接收机和第二差分接收机耦合到相同的两个终端，当差分信号使用第一类型的差分时，使用第一差分接收机 信号编码时，当差分信号使用第二类型的差分信号编码时，使用第二差分接收机。

公开(公告)号：US20140254732A1

公开(公告)日：2014-09-11

申请号：US14199898

申请日：2014-03-06

Applicant: QUALCOMM INCORPORATED

Inventor： Shoichiro Sengoku ,  George Alan Wiley ,  Chulkyu Lee ,  Joseph Cheung

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H03K5/1252 ,  H03K5/1534 ,  H04L7/0066 ,  H04L7/027 ,  H04L25/0272 ,  H04L25/14 ,  H04L25/49 ,  H04L25/4906 ,  H04L25/493

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract translation: 提供了一种用于执行多线信令编码的方法，其中在符号转换内对时钟信号进行编码。 数据位序列被转换成多个m个转换数。 每个转换编号从一组顺序符号编号转换成顺序符号。 顺序符号号被转换成可以通过多个差分驱动器发送的原始符号。 原始符号被传播扩展到多条n线，其中时钟信号被有效地嵌入到原始符号的传输中，因为从转换数转换为顺序符号，从而确保没有两个连续的原始符号相同。 原始符号保证在多条n线的所有对上具有非零的差分电压。

公开(公告)号：US20190149314A1

公开(公告)日：2019-05-16

申请号：US16243647

申请日：2019-01-09

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L7/00 ,  H03K5/1534 ,  H03K5/13 ,  G06F1/12 ,  H04L7/033 ,  H04L25/49 ,  H03K5/133

CPC classification number: H04L7/0045 ,  G06F1/12 ,  H03K5/13 ,  H03K5/133 ,  H03K5/1534 ,  H04L7/0037 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/49

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.

公开(公告)号：US10218492B2

公开(公告)日：2019-02-26

申请号：US15470479

申请日：2017-03-27

Applicant: QUALCOMM Incorporated

Inventor： Shoichiro Sengoku

IPC: H04L25/49 ,  H04L7/00 ,  H04L7/033 ,  G06F1/12 ,  H03K5/133 ,  H03K5/13 ,  H03K5/1534

Abstract: A method and an apparatus are provided. The apparatus may include a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.