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    Kernel masking of DRAM defects
    11.
    发明授权
    Kernel masking of DRAM defects 有权
    DRAM缺陷的内核屏蔽

    公开(公告)号：US09299457B2

    公开(公告)日：2016-03-29

    申请号：US14187279

    申请日：2014-02-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： Dexter T. Chun ,  Yanru Li ,  Xiangyu Dong ,  Jungwon Suh ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

    IPC: G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02

    CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

    Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

    Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。

    Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems
    12.
    发明授权
    Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems 有权
    异构存储器系统以及用于在基于处理器的系统中支持异构存储器访问请求的相关方法和计算机可读介质

    公开(公告)号：US09224452B2

    公开(公告)日：2015-12-29

    申请号：US13743400

    申请日：2013-01-17

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F13/16 ,  G06F12/08 ,  G11C11/406

    CPC classification number: G11C11/40603 ,  G06F12/08 ,  G06F13/1694 ,  Y02D10/14

    Abstract: Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems are disclosed. A heterogeneous memory system is comprised of a plurality of homogeneous memories that can be accessed for a given memory access request. Each homogeneous memory has particular power and performance characteristics. In this regard, a memory access request can be advantageously routed to one of the homogeneous memories in the heterogeneous memory system based on the memory access request, and power and/or performance considerations. The heterogeneous memory access request policies may be predefined or determined dynamically based on key operational parameters, such as read/write type, frequency of page hits, and memory traffic, as non-limiting examples. In this manner, memory access request times can be optimized to be reduced without the need to make tradeoffs associated with only having one memory type available for storage.

    Abstract translation: 公开了用于在基于处理器的系统中支持异构存储器访问请求的异构存储器系统以及相关方法和计算机可读介质。 异构存储器系统由可以针对给定存储器访问请求访问的多个均匀存储器组成。 每个均匀存储器具有特定的功率和性能特性。 在这方面，存储器访问请求可以有利地基于存储器访问请求以及功率和/或性能考虑路由到异构存储器系统中的同构存储器之一。 作为非限制性示例，异类存储器访问请求策略可以基于诸如读/写类型，页面命中的频率和存储器流量的关键操作参数动态地预定义或确定。 以这种方式，存储器访问请求时间可以被优化以被减少，而不需要进行与仅具有可用于存储的一个存储器类型相关联的权衡。

    Read operation of MRAM using a dummy word line
    15.
    发明授权
    Read operation of MRAM using a dummy word line 有权
    使用虚拟字线读取MRAM的操作

    公开(公告)号：US09275714B1

    公开(公告)日：2016-03-01

    申请号：US14499050

    申请日：2014-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Taehyun Kim ,  Sungryul Kim ,  Jung Pill Kim ,  Xiangyu Dong

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1693

    Abstract: Systems and methods relate to a read operation on a magnetoresistive random access memory (MRAM). Prior to determining whether there is a hit in the MRAM for a first address corresponding to the read operation, a dummy word line is activated, based on at least a subset of bits of the first address. A settling process for a reference voltage for reading MRAM bit cells at the first address is initiated, based on dummy cells connected to the dummy word line and a settled reference voltage is obtained. If there is a hit, a first word line is activated based on a row address determined from the first address, and the MRAM bit cells at the first address are read using the settled reference voltage.

    Abstract translation: 系统和方法涉及磁阻随机存取存储器（MRAM）上的读取操作。 在确定MRAM中是否存在与读取操作相对应的第一地址的命中之前，基于第一地址的位的至少一个子集，激活伪字线。 基于与虚拟字线连接的虚拟单元，启动用于读取第一地址的MRAM位单元的参考电压的稳定处理，并获得稳定的参考电压。 如果存在命中，则基于从第一地址确定的行地址来激活第一字线，并且使用稳定的参考电压读取第一地址处的MRAM位单元。

    INTEGRATED MRAM MODULE
    18.
    发明申请
    INTEGRATED MRAM MODULE 有权
    集成MRAM模块

    公开(公告)号：US20140177325A1

    公开(公告)日：2014-06-26

    申请号：US13721092

    申请日：2012-12-20

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Jungwon Suh

    IPC: G11C11/16

    CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C2211/5643 ,  Y10T29/49117

    Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

    Abstract translation: 用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。 集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或 多个包装。 第二包还包括存储器控制器逻辑。 简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的封印能力。

    System and method to defragment a memory
    19.
    发明授权
    System and method to defragment a memory 有权
    系统和方法来对内存进行碎片整理

    公开(公告)号：US09436606B2

    公开(公告)日：2016-09-06

    申请号：US14146576

    申请日：2014-01-02

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jungwon Suh

    IPC: G06F12/08 ,  G06F12/10 ,  G06F3/06

    CPC classification number: G06F12/0833 ,  G06F3/0608 ,  G06F12/0873 ,  G06F12/0895 ,  G06F12/12 ,  G06F2206/1004 ,  Y02D10/13

    Abstract: A system and method to defragment a memory is disclosed. In a particular embodiment, a method includes loading data stored at a first physical memory address of a memory from the memory into a cache line of a data cache. The first physical memory address is mapped to a first virtual memory address. The method further includes initiating modification, at the data cache, of lookup information associated with the first virtual memory address so that the first virtual memory address corresponds to a second physical memory address of the memory. The method also includes modifying, at the data cache, information associated with the cache line to indicate that the cache line corresponds to the second physical memory address instead of the first physical memory address.

    Abstract translation: 公开了一种用于对存储器进行碎片整理的系统和方法。 在特定实施例中，一种方法包括将存储在存储器的第一物理存储器地址上的数据从存储器加载到数据高速缓存的高速缓存行中。 第一个物理内存地址映射到第一个虚拟内存地址。 该方法还包括在数据高速缓存处启动与第一虚拟存储器地址相关联的查找信息的修改，使得第一虚拟存储器地址对应于存储器的第二物理存储器地址。 该方法还包括在数据高速缓存处修改与高速缓存行相关联的信息，以指示高速缓存线对应于第二物理存储器地址而不是第一物理存储器地址。

    Integrated MRAM module
    20.
    发明授权
    Integrated MRAM module 有权
    集成MRAM模块

    公开(公告)号：US09378793B2

    公开(公告)日：2016-06-28

    申请号：US13721092

    申请日：2012-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Xiangyu Dong ,  Jung Pill Kim ,  Jungwon Suh

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/16 ,  G11C11/1653 ,  G11C2211/5643 ,  Y10T29/49117

    Abstract: Systems and methods for integrated magnetoresistive random access memory (MRAM) modules. An integrated circuit includes a processor without a last level cache integrated on a first chip a MRAM module comprising a MRAM last level cache and a MRAM main memory integrated on a second chip, wherein the MRAM module is a unified structure fabricated as monolithic package or a plurality of packages. The second package further includes memory controller logic. A simplified interface structure is configured to couple the first and the second package. The MRAM module is designed for high speed, high data retention, aggressive prefetching between the MRAM last level cache and the MRAM main memory, improved page handling, and improved seal ability.

    Abstract translation: 用于集成磁阻随机存取存储器（MRAM）模块的系统和方法。 集成电路包括处理器，其中没有集成在第一芯片上的最后一级高速缓存，MRAM模块包括MRAM最后一级高速缓存和集成在第二芯片上的MRAM主存储器，其中MRAM模块是制造为单片封装或 多个包装。 第二包还包括存储器控制器逻辑。 简化的接口结构被配置为耦合第一和第二封装。 MRAM模块设计用于高速，高数据保留，MRAM最后一级缓存和MRAM主内存之间的积极预取，改进的页面处理和改进的密封能力。

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