公开(公告)号：US20160155748A1

公开(公告)日：2016-06-02

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jeffrey Junhao XU ,  Zhongze WANG ,  Bin YANG ,  Xiaonan CHEN ,  Yu LU

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，被实现为非易失性存储器件中的铁电偶极子层

公开(公告)号：US20160079307A1

公开(公告)日：2016-03-17

申请号：US14483919

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Yu LU

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar.

公开(公告)号：US20160043304A1

公开(公告)日：2016-02-11

申请号：US14454509

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Wei-Chuan CHEN ,  Xiaochun ZHU ,  Xia LI ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L43/02

CPC classification number: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A perpendicular magnetic tunnel junction (pMTJ) device includes a perpendicular reference layer, a tunnel barrier layer on a surface of the perpendicular reference layer, and a perpendicular free layer on a surface of the tunnel barrier layer. The pMTJ device also includes a dielectric passivation layer on the tunnel barrier layer and surrounding the perpendicular free layer. The pMTJ device further includes a high permeability material on the dielectric passivation layer that is configured to be magnetized by the perpendicular reference layer and to provide a stray field to the perpendicular free layer that compensates for a stray field from the perpendicular reference layer.

Abstract translation: 垂直磁隧道结（pMTJ）器件包括垂直参考层，垂直参考层表面上的隧道势垒层和隧道势垒层表面上的垂直自由层。 pMTJ器件还包括在隧道势垒层上的电介质钝化层并围绕垂直自由层。 pMTJ器件还包括介电钝化层上的高磁导率材料，其被配置为由垂直参考层磁化，并且向垂直自由层提供杂散场，该杂散场补偿来自垂直参考层的杂散场。

公开(公告)号：US20160020250A1

公开(公告)日：2016-01-21

申请号：US14334554

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Wei-Chuan CHEN ,  Yu LU ,  Kangho LEE ,  Seung Hyuk KANG

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L27/224 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/73 ,  H01L27/228 ,  H01L43/08

Abstract: An MRAM cell may include a magnetic tunneling junction (MTJ). The MTJ includes a pin layer, a barrier layer, a free layer, and a capping layer. The MRAM cell further includes a bidirectional diode selector, directly coupled to an electrode of the MTJ, to enable access to the MTJ.

Abstract translation: MRAM单元可以包括磁隧道结（MTJ）。 MTJ包括针层，阻挡层，自由层和覆盖层。 MRAM单元还包括直接耦合到MTJ的电极的双向二极管选择器，以使得能够访问MTJ。

公开(公告)号：US20150311429A1

公开(公告)日：2015-10-29

申请号：US14795799

申请日：2015-07-09

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

Abstract translation: 提供了一种改进的磁性隧道结装置和用于制造改进的磁性隧道结装置的方法。 所提供的双蚀刻工艺减少蚀刻损伤和烧蚀材料再沉积。 在一个实例中，提供了一种用于制造磁性隧道结（MTJ）的方法。 该方法包括在衬底上形成缓冲层，在衬底上形成底电极，在底电极上形成引脚层，在引脚层上形成阻挡层，并在阻挡层上形成自由层。 第一蚀刻包括蚀刻自由层，而不蚀刻阻挡层，引脚层和底部电极。 该方法还包括在自由层上形成顶部电极，以及在顶部电极上形成硬掩模层。 第二蚀刻包括蚀刻硬掩模层; 顶部电极层，阻挡层，针层和底部电极。

公开(公告)号：US20150287910A1

公开(公告)日：2015-10-08

申请号：US14243324

申请日：2014-04-02

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Chando PARK ,  Wei-Chuan CHEN

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

Abstract translation: 用于制造磁性隧道结（MTJ）装置的多步骤蚀刻技术包括在第一蚀刻步骤中在MTJ装置的第一电极上形成第一导电硬掩模以蚀刻第一电极。 该方法还包括在第一导电硬掩模上形成第二导电硬掩模，用于在第二蚀刻步骤期间蚀刻MTJ装置的磁性层。 间隔层共形沉积在第一导电硬掩模的侧壁上。 第二导电硬掩模沉积在第一导电硬掩模上并与第一导电硬掩模的侧壁上的间隔层对准。

公开(公告)号：US20150280112A1

公开(公告)日：2015-10-01

申请号：US14229427

申请日：2014-03-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Kangho LEE ,  Wei-Chuan CHEN ,  Yu LU ,  Chando PARK ,  Seung Hyuk KANG

IPC: H01L43/12 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/222 ,  H01L27/224 ,  H01L43/08 ,  H01L43/12

Abstract: An improved magnetic tunnel junction device and methods for fabricating the improved magnetic tunnel junction device are provided. The provided two-etch process reduces etching damage and ablated material redeposition. In an example, provided is a method for fabricating a magnetic tunnel junction (MTJ). The method includes forming a buffer layer on a substrate, forming a bottom electrode on the substrate, forming a pin layer on the bottom electrode, forming a barrier layer on the pin layer, and forming a free layer on the barrier layer. A first etching includes etching the free layer, without etching the barrier layer, the pin layer, and the bottom electrode. The method also includes forming a top electrode on the free layer, as well as forming a hardmask layer on the top electrode. A second etching includes etching the hardmask layer; the top electrode layer, the barrier layer, the pin layer, and the bottom electrode.

公开(公告)号：US20150249209A1

公开(公告)日：2015-09-03

申请号：US14195566

申请日：2014-03-03

Applicant: QUALCOMM Incorporated

Inventor： Yu LU ,  Xia LI ,  Seung Hyuk KANG ,  Shiqun GU

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L21/76802 ,  H01L21/76813 ,  H01L21/76832 ,  H01L27/222 ,  H01L43/02 ,  H01L43/08

Abstract: Systems and methods for forming precise and self-aligned top metal contact for a Magnetoresistive random-access memory (MRAM) device include forming a magnetic tunnel junction (MTJ) in a common interlayer metal dielectric (IMD) layer with a logic element. A low dielectric constant (K) etch stop layer is selectively retained over an exposed top surface of the MTJ. Etching is selectively performed through a top IMD layer formed over the low K etch stop layer and the common IMD layer, based on a first chemistry which prevents etching through the low K etch stop layer. By switching chemistry to a second chemistry which precisely etches through the low K etch stop layer, an opening is created for forming a self-aligned top contact to the exposed top surface of the MTJ.

Abstract translation: 用于形成用于磁阻随机存取存储器（MRAM）器件的精确和自对准的顶部金属接触的系统和方法包括在具有逻辑元件的公共层间金属电介质（IMD）层中形成磁性隧道结（MTJ）。 低介电常数（K）蚀刻停止层选择性地保留在MTJ的暴露的顶表面上。 基于防止蚀刻通过低K蚀刻停止层的第一化学反应，通过形成在低K蚀刻停止层和公共IMD层上的顶部IMD层选择性地进行蚀刻。 通过将化学转换成精确地蚀刻通过低K蚀刻停止层的第二化学物质，形成一个开口以形成与MTJ暴露的顶表面的自对准顶部接触。