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    MAGNETRESISTIVE RANDOM-ACCESS MEMORY AND FABRICATION METHOD THEREOF
    1.
    发明申请
    MAGNETRESISTIVE RANDOM-ACCESS MEMORY AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：US20170084819A1

    公开(公告)日：2017-03-23

    申请号：US14859278

    申请日：2015-09-19

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

    CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

    Abstract: Provided are exemplary circuits including a magnetoresistive random-access memory (MRAM) and methods for fabricating the circuits. In an example, a circuit includes an MRAM. The circuit includes a bottom interconnect in a bottom interconnect level. The bottom interconnect is configured to route a signal outside of a magnetic tunnel junction (MTJ) stack. The circuit includes the MTJ stack formed on a bottom electrode at least partially embedded in the bottom interconnect level. Optionally, the circuit also includes an encapsulation layer encapsulating at least a portion of the MTJ stack. The encapsulation layer is also an electromigration cap for a second bottom interconnect in the bottom interconnect level. The second bottom interconnect is a not part of the MTJ stack. Optionally, the bottom electrode is self-aligned with the bottom interconnect.

    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) INTEGRATION WITH TOP CONTACTS
    2.
    发明申请
    EMBEDDED MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) INTEGRATION WITH TOP CONTACTS 有权
    嵌入式磁阻随机访问存储器（MRAM）与顶级联系人集成

    公开(公告)号：US20160133828A1

    公开(公告)日：2016-05-12

    申请号：US14625494

    申请日：2015-02-18

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/08 ,  H01L43/12 ,  H01L43/02

    CPC classification number: H01L43/08 ,  H01L27/222 ,  H01L43/02 ,  H01L43/12

    Abstract: A magnetoresistive random access memory (MRAM) device includes a top electrode or top contact above a metal hard mask which has a limited height due to process limitations in advanced nodes. The metal hard mask is provided on a magnetic tunnel junction (MTJ). The top contact for the MTJ is formed within a dielectric layer, such as a low dielectric constant (low-k) or extremely low-k layer. An additional dielectric layer is provided above the top contact for additional connections for additional circuitry to form a three-dimensional integrated circuit (3D IC).

    Abstract translation: 磁阻随机存取存储器（MRAM）装置包括金属硬掩模上方的顶部电极或顶部触点，由于先进节点中的工艺限制，其具有有限的高度。 金属硬掩模设置在磁性隧道结（MTJ）上。 MTJ的顶部接触形成在介电层内，例如低介电常数（低k）或极低k层。 在顶部触点上方提供了另外的介电层，用于额外的连接，用于附加电路以形成三维集成电路（3D IC）。

    MRAM INTEGRATION TECHNIQUES FOR TECHNOLOGY SCALING
    3.
    发明申请
    MRAM INTEGRATION TECHNIQUES FOR TECHNOLOGY SCALING 有权
    技术规模化MRAM集成技术

    公开(公告)号：US20160329488A1

    公开(公告)日：2016-11-10

    申请号：US15213384

    申请日：2016-07-18

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Yu LU ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08

    CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

    Abstract translation: 与收缩装置技术兼容的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共夹层金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

    MRAM INTEGRATION WITH LOW-K INTER-METAL DIELECTRIC FOR REDUCED PARASITIC CAPACITANCE
    5.
    发明申请
    MRAM INTEGRATION WITH LOW-K INTER-METAL DIELECTRIC FOR REDUCED PARASITIC CAPACITANCE 有权
    具有低K金属间电介质的MRAM集成用于降低PARASIIC电容

    公开(公告)号：US20160093668A1

    公开(公告)日：2016-03-31

    申请号：US14496525

    申请日：2014-09-25

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Xia LI ,  Seung Hyuk KANG

    IPC: H01L27/22 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L45/02 ,  H01L45/00

    CPC classification number: H01L27/222 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01L45/02 ,  H01L45/08 ,  H01L45/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Systems and methods of integration of resistive memory elements with logic elements in advanced nodes with improved mechanical stability and reduced parasitic capacitance include a resistive memory element and a logic element formed in a common integration layer extending between a bottom cap layer and a top cap layer. At least a first intermetal dielectric (IMD) layer of high-K value is formed in the common integration layer and surrounding at least the resistive memory element, to provide high rigidity and mechanical stability. A second IMD layer of low-K value to reduce parasitic capacitance of the logic element is formed in either the common integration layer, a top layer above the top cap layer or an intermediate layer in between the top and bottom cap layers. Air gaps may be formed in one or more IMD layers to further reduce capacitance.

    Abstract translation: 电阻式存储器元件与具有改进的机械稳定性和减小的寄生电容的先进节点中的逻辑元件的集成的系统和方法包括形成在底盖层和顶盖层之间延伸的公共集成层中的电阻存储元件和逻辑元件。 至少在公共积分层中形成高K值的第一金属间电介质（IMD）层，并且至少围绕电阻式存储元件，以提供高刚性和机械稳定性。 降低逻辑元件的寄生电容的低K值的第二IMD层形成在公共集成层，顶盖层上的顶层或顶盖层之间的中间层。 可以在一个或多个IMD层中形成气隙，以进一步降低电容。

    REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH
    6.
    发明申请
    REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH 审中-公开

    公开(公告)号：US20160133833A1

    公开(公告)日：2016-05-12

    申请号：US14995193

    申请日：2016-01-13

    Applicant: QUALCOMM INCORPORATED

    Inventor： Yu LU ,  Chando PARK ,  Wei-Chuan CHEN

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08

    CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08

    Abstract: A multi-step etch technique for fabricating a magnetic tunnel junction (MTJ) apparatus includes forming a first conductive hard mask on a first electrode of the MTJ apparatus for etching the first electrode during a first etching step. The method also includes forming a second conductive hard mask on the first conductive hard mask for etching magnetic layers of the MTJ apparatus during a second etching step. A spacer layer is conformally deposited on sidewalls of the first conductive hard mask. The second conductive hard mask is deposited on the first conductive hard mask and aligned with the spacer layer on the sidewalls of the first conductive hard mask.

    MRAM INTEGRATION TECHNIQUES FOR TECHNOLOGY
    8.
    发明申请
    MRAM INTEGRATION TECHNIQUES FOR TECHNOLOGY 有权
    MRAM技术集成技术

    公开(公告)号：US20150171314A1

    公开(公告)日：2015-06-18

    申请号：US14109200

    申请日：2013-12-17

    Applicant: QUALCOMM Incorporated

    Inventor： Xia LI ,  Yu LU ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

    CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: A magnetoresistive random-access memory (MRAM) integration compatible with shrinking device technologies includes a magnetic tunnel junction (MTJ) formed in a common interlayer metal dielectric (IMD) layer with one or more logic elements. The MTJ is connected to a bottom metal line in a bottom IMD layer and a top via connected to a top IMD layer. The MTJ substantially extends between one or more bottom cap layers configured to separate the common IMD layer and the bottom IMD layer and one or more top cap layers configured to separate the common IMD layer and the top IMD layer. The MTJ can include a top electrode to connect to the top via or be directly connected to the top via through a hard mask for smaller device technologies. The logic elements include vias, metal lines, and semiconductor devices.

    Abstract translation: 兼容收缩器件技术的磁阻随机存取存储器（MRAM）集成包括形成在具有一个或多个逻辑元件的公共层间金属电介质（IMD）层中的磁性隧道结（MTJ）。 MTJ连接到底部IMD层中的底部金属线和连接到顶部IMD层的顶部通孔。 MTJ基本上在配置成分离公共IMD层和底部IMD层的一个或多个底盖层之间延伸，以及被配置为分离公共IMD层和顶部IMD层的一个或多个顶盖层。 MTJ可以包括顶部电极，以连接到顶部通孔，或者通过用于较小器件技术的硬掩模直接连接到顶部通孔。 逻辑元件包括通孔，金属线和半导体器件。

    DE-INTEGRATED TRENCH FORMATION FOR ADVANCED MRAM INTEGRATION
    9.
    发明申请
    DE-INTEGRATED TRENCH FORMATION FOR ADVANCED MRAM INTEGRATION 有权
    用于高级MRAM集成的集成化梯度形成

    公开(公告)号：US20160365505A1

    公开(公告)日：2016-12-15

    申请号：US14735006

    申请日：2015-06-09

    Applicant: QUALCOMM Incorporated

    Inventor： Yu LU ,  Wei-Chuan CHEN ,  Seung Hyuk KANG

    IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

    Abstract: A semiconductor device may include a magnetoresistive random-access memory (MRAM) trench having a first conductive barrier liner and a second conductive barrier liner. The MRAM trench may land on a hard mask of a magnetic tunnel junction (MTJ) within an MTJ region of the semiconductor device. The semiconductor device may also include a logic trench having the first conductive barrier liner. The semiconductor device may further include a logic via having the first conductive barrier liner. The logic via may land on a first portion of a conductive interconnect (Mx) within a logic region of the semiconductor device.

    Abstract translation: 半导体器件可以包括具有第一导电阻挡衬垫和第二导电阻挡衬里的磁阻随机存取存储器（MRAM）沟槽。 MRAM沟槽可以落在半导体器件的MTJ区域内的磁性隧道结（MTJ）的硬掩模上。 半导体器件还可以包括具有第一导电阻挡衬里的逻辑沟槽。 半导体器件还可以包括具有第一导电阻挡衬里的逻辑通孔。 逻辑通孔可以落在半导体器件的逻辑区域内的导电互连（Mx）的第一部分上。

    SUB-LITHOGRAPHIC PATTERNING OF MAGNETIC TUNNELING JUNCTION DEVICES
    10.
    发明申请
    SUB-LITHOGRAPHIC PATTERNING OF MAGNETIC TUNNELING JUNCTION DEVICES 有权
    磁悬浮连接装置的分层图案

    公开(公告)号：US20160254446A1

    公开(公告)日：2016-09-01

    申请号：US15149004

    申请日：2016-05-06

    Applicant: QUALCOMM INCORPORATED

    Inventor： Yu LU

    IPC: H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22

    CPC classification number: H01L43/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    Abstract: A method for fabricating a magnetic tunnel junction (MTJ) device includes creating a recess within a second patterning layer, in which a first patterning layer overhangs the recessed second patterning layer. Such a method further includes depositing a film into the recess to create a keyhole pattern within the deposited film. The method further includes transferring the keyhole pattern through a hard mask layer to an MTJ stack. The method also includes depositing a conductive material into the transferred keyhole pattern and on an MTJ stack. The method also includes removing the hard mask layer to create a conductive hard mask pillar.

    Abstract translation: 一种用于制造磁性隧道结（MTJ）器件的方法包括在第二图案化层内形成凹陷，其中第一图案化层突出于凹陷的第二图案形成层。 这种方法还包括将膜沉积到凹槽中以在沉积的膜内产生锁孔图案。 该方法还包括将锁孔图案通过硬掩模层转移到MTJ堆叠。 该方法还包括将导电材料沉积到转移的锁孔图案中和在MTJ堆叠上。 该方法还包括去除硬掩模层以形成导电硬掩模支柱。

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