公开(公告)号：US10795830B2

公开(公告)日：2020-10-06

申请号：US16041645

申请日：2018-07-20

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Yanru Li

IPC: G06F12/14 ,  G06F21/79 ,  G11C8/10

Abstract: In conventional memory systems, no access control is performed when write-x and datacopy0 are issued. To address this issue, it is proposed to provide access control to these commands by leveraging the mechanism to enforce access control to normal write commands so that the mechanism is also applied to the write-x and datacopy0 commands.

公开(公告)号：US10726904B2

公开(公告)日：2020-07-28

申请号：US16362427

申请日：2019-03-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C13/06 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US10591975B2

公开(公告)日：2020-03-17

申请号：US15798116

申请日：2017-10-30

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Azzedine Touzni ,  Dexter Tamio Chun

IPC: G06F1/32 ,  G06F1/3246 ,  G06F15/78 ,  G06F1/3234 ,  G06F9/4401 ,  G06F21/81 ,  G06F1/3287 ,  G06F21/79 ,  G06F21/57

Abstract: Systems and methods are disclosed for managing memory access for low-power use cases of a system on chip. One such method comprises booting a system on chip (SoC) comprising a plurality of SoC processing devices. A trusted channel is created to a secure non-volatile random access memory (NVRAM). The method determines a power-saving software program to be executed on the SoC by one of the plurality of SoC processing devices. A software image associated with the power-saving software program is loaded to the secure NVRAM. In response to loading the software image to the secure NVRAM, each of the plurality of SoC processing devices except the one executing the software image from the secure NVRAM are powered down.

公开(公告)号：US10157008B2

公开(公告)日：2018-12-18

申请号：US14699431

申请日：2015-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li

IPC: G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F12/06 ,  G06F9/4401

Abstract: Systems, methods, and computer programs are disclosed for providing a heterogeneous system memory in a portable communication device. One system comprises a system on chip (SoC) coupled to a nonvolatile random access memory (NVRAM) and a volatile random access memory (VRAM). The SoC comprises an operating system for mapping a heterogeneous system memory comprising the NVRAM and the VRAM. The operating system comprises a memory manager configured to allocate a first portion of the NVRAM as a block device for a swap operation, a second portion of the NVRAM for program code and read-only data, and a third portion of the NVRAM for operating system page tables. The VRAM is allocated for a program heap and a program stack.

公开(公告)号：US09928924B2

公开(公告)日：2018-03-27

申请号：US14970273

申请日：2015-12-15

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter Tamio Chun ,  Yanru Li

IPC: G11C29/42 ,  G06F11/10 ,  G06F12/02 ,  G06F13/24 ,  G11C7/10 ,  G06F12/08 ,  G06F12/0875

CPC classification number: G11C29/42 ,  G06F11/1016 ,  G06F11/1048 ,  G06F11/1064 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/0875 ,  G06F13/24 ,  G11C7/1072

Abstract: Systems, methods, and computer programs are disclosed for resolving dynamic random access memory (DRAM) defects. One embodiment is a system comprising a dynamic random access memory (DRAM) system electrically coupled to a system on chip (SoC). The SoC comprises a cache and a cache controller. The cache controller is configured to store corrected data for a failed physical codeword address associated with the DRAM in the cache and provide further access to the failed physical codeword address from the cache instead of the DRAM system.

公开(公告)号：US09812222B2

公开(公告)日：2017-11-07

申请号：US14691570

申请日：2015-04-20

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Dexter Tamio Chun ,  Jungwon Suh ,  Deepti Vijayalakshmi Sriramagiri ,  Yanru Li ,  Mosaddiq Saifuddin ,  Xiangyu Dong

IPC: G06F11/00 ,  G11C29/44 ,  G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G11C29/42 ,  G11C11/401

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C11/401 ,  G11C29/42 ,  G11C29/76

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

公开(公告)号：US09418033B2

公开(公告)日：2016-08-16

申请号：US14337904

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Terrence Brian Remple ,  Devdutt Patnaik ,  Jay Yu Jae Choi ,  Yanru Li

IPC: G06F3/00 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4291

Abstract: A method of triggering a desired operating mode in a universal serial bus (USB)-compatible client device is provided. A USB-compatible client device detects that it has been coupled to a USB-compatible host device via a USB bus. The USB-compatible client device attempts to pull a data line of the USB bus high. The USB-compatible client device then ascertains that the data line remains pulled low, thereby indicating that the USB-compatible client device should enter a first mode of operation. The USB-compatible client device operates according to the first mode of operation.

Abstract translation: 提供了一种在通用串行总线（USB）兼容客户端设备中触发所需操作模式的方法。 USB兼容的客户端设备通过USB总线检测到它已经耦合到与USB兼容的主机设备。 USB兼容客户端设备尝试将USB总线的数据线拉高。 USB兼容的客户端设备然后确定数据线保持拉低，从而指示USB兼容的客户端设备应该进入第一操作模式。 USB兼容客户端设备根据第一种操作模式进行操作。

公开(公告)号：US11164618B2

公开(公告)日：2021-11-02

申请号：US16907103

申请日：2020-06-19

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

IPC: G11C5/00 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

公开(公告)号：US10956057B2

公开(公告)日：2021-03-23

申请号：US16115845

申请日：2018-08-29

Applicant: QUALCOMM Incorporated

Inventor： Yanru Li ,  Dexter Tamio Chun

IPC: G06F3/06

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of controlling a memory of a computing device by an adaptive memory controller. The method includes collecting usage data from the computing device over a first bin, wherein the first bin is associated with a first weight, wherein the first weight is indicative of one or more of a first partial array self-refresh (PASR) setting a first partial array auto refresh (PAAR) setting and a first deep power down (DPD) setting. The method further includes associating the collected data with a second weight, adapting the first bin based on the second weight, wherein the second weight is indicative of one or more of a second PASR, PAAR, and DPD setting. The method further includes controlling the memory during the next first bin based on the second weight.

公开(公告)号：US20200098420A1

公开(公告)日：2020-03-26

申请号：US16137496

申请日：2018-09-20

Applicant: QUALCOMM INCORPORATED

Inventor： Yanru Li ,  Dexter Chun ,  Pratik Patel

IPC: G11C11/406 ,  G06F3/06

Abstract: Systems, methods, and computer programs are disclosed for refreshing a volatile memory. An embodiment of a method comprises storing, in a volatile memory device comprising a cell array having a plurality of rows with a correspond ng row address, a table specifying one of a data valid indicator and a data invalid indicator for each of the plurality of row addresses. The data valid indicator specifies that the corresponding row is in use, and the data invalid indicator specifies that the corresponding row is not in use. A memory controller initiates a refresh command. In response to the refresh command, the rows having the data valid indicator are refreshed while the rows having the data invalid indicator are skipped.