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公开(公告)号：US20160126983A1
公开(公告)日：2016-05-05
申请号：US14532309
申请日：2014-11-04
发明人： Abbas Komijani , Mohammad Bagher Vahid Far , Amirpouya Kavousian , Alireza Khalili , Yashar Rajavi
CPC分类号： H04B1/0064 , H04B1/16 , H04B5/0031 , H04B5/0087 , H04B5/0093
摘要： A multi-band amplifier may operate in a first frequency band and a second frequency band. The multi-band amplifier may include a first amplifier, a second amplifier, and a coupler. The coupler may couple a signal, such as a communication signal, to a selected amplifier. In some embodiments, the coupler may include one or more inductive elements to couple the signal to the first or the second amplifier. In some embodiments, the inductive elements may include a balun.
摘要翻译： 多频带放大器可以在第一频带和第二频带中操作。 多频带放大器可以包括第一放大器，第二放大器和耦合器。 耦合器可以将诸如通信信号的信号耦合到所选择的放大器。 在一些实施例中，耦合器可以包括一个或多个感应元件以将信号耦合到第一或第二放大器。 在一些实施例中，感应元件可包括平衡 - 不平衡转换器。
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公开(公告)号：US09160584B1
公开(公告)日：2015-10-13
申请号：US14603127
申请日：2015-01-22
发明人： Amirpouya Kavousian , Yashar Rajavi , Richard Tzewei Chang , Alireza Khalili , Mohammad Bagher Vahid Far , Abbas Komijani
摘要： A method and apparatus are disclosed for mitigating a frequency spur included with a transmitter output signal from a wireless device. For at least some embodiments, the wireless device may include an auxiliary synthesizer to generate a spur cancellation signal to be summed with the transmitter output signal to cancel or reduce the frequency spur. The auxiliary synthesizer may also generate an auxiliary clock signal to demodulate a received communication signal. In some embodiments, the transmitter output signal may be looped back to a receiver of the wireless device to determine whether the frequency spur is reduced below a threshold. Data from the receiver may be used to modify the spur cancellation signal.
摘要翻译： 公开了一种用于减轻来自无线设备的发射机输出信号所包含的频率支路的方法和装置。 对于至少一些实施例，无线设备可以包括辅助合成器，以产生要与发射机输出信号相加的杂散消除信号，以消除或减少频率突发。 辅助合成器还可以产生辅助时钟信号以解调所接收的通信信号。 在一些实施例中，发射机输出信号可以环回到无线设备的接收机，以确定频率突发是否减小到低于阈值。 来自接收机的数据可以用于修改杂散消除信号。
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公开(公告)号：US09077445B2
公开(公告)日：2015-07-07
申请号：US13939076
申请日：2013-07-10
IPC分类号： H04B1/38 , H04B17/00 , H04B17/10 , H04B17/11 , H04B17/16 , H04B17/318 , H04B17/345 , G01R21/01
CPC分类号： H04B17/318 , G01R21/01 , H04B17/104 , H04B17/11 , H04B17/16 , H04B17/345
摘要： A temperature compensated RF peak detector is disclosed. In an exemplary embodiment, an apparatus includes a first RF peak detector configured to generate a reference signal, a temperature compensated threshold generator configured to generate a temperature compensated detection threshold based on the reference signal, and a comparator configured to generate a peak detection output based on the temperature compensated detection threshold.
摘要翻译： 公开了一种温度补偿RF峰值检测器。 在示例性实施例中，一种装置包括被配置为产生参考信号的第一RF峰值检测器，被配置为基于参考信号产生温度补偿检测阈值的温度补偿阈值发生器，以及配置成基于参考信号产生基于峰值检测输出的比较器 对温度补偿检测阈值。
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公开(公告)号：US08736329B1
公开(公告)日：2014-05-27
申请号：US13760896
申请日：2013-02-06
IPC分类号： H03K3/017
CPC分类号： G06F1/04 , H03K5/1565
摘要： Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.
摘要翻译： 公开了包括具有两个定时器电路以测量时钟信号的脉冲宽度的占空比模块的系统和方法。 两个比较器用于根据脉冲宽度测量的比较来产生控制信号。 响应于控制信号，时钟信号或反相时钟信号可以可编程地延迟，使得时钟信号和反相时钟信号的组合导致校正的时钟信号。 还公开了用于验证占空比模块的操作的系统和方法。
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公开(公告)号：US10608583B2
公开(公告)日：2020-03-31
申请号：US15638183
申请日：2017-06-29
摘要： Certain aspects of the present disclosure provide methods and apparatus for reducing phase noise in voltage-controlled oscillators (VCOs). One example VCO generally includes a first resonant circuit comprising an inductor and a first variable capacitive element coupled in parallel with the inductor; and a second variable capacitive element coupled to a center tap of the inductor and further coupled to a reference voltage, wherein the center tap of the inductor is further coupled to a voltage source.
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公开(公告)号：US10128823B2
公开(公告)日：2018-11-13
申请号：US14642309
申请日：2015-03-09
摘要： Certain aspects of the present disclosure generally relate to generating a large electrical resistance. One example circuit generally includes a first transistor having a gate, a source connected with a first node of the circuit, and a drain connected with a second node of the circuit. The circuit may also include a voltage-limiting device connected between the gate and the source of the first transistor, wherein the device, if forward biased, is configured to limit a gate-to-source voltage of the first transistor such that the first transistor operates in a sub-threshold region. The circuit may further include a second transistor configured to bias the voltage-limiting device with a current, wherein a drain of the second transistor is connected with the gate of the first transistor, a gate of the second transistor is connected with the first node, and a source of the second transistor is connected with an electric potential.
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公开(公告)号：US09800249B2
公开(公告)日：2017-10-24
申请号：US15051156
申请日：2016-02-23
发明人： Yashar Rajavi , Jeongsik Yang , Emilia Vailun Lei
CPC分类号： H03K21/026 , H03K3/0372 , H03K3/3562 , H03L7/08
摘要： The present disclosure describes current steering phase control for current-mode logic (CML) circuits. In some aspects, a circuit for frequency division comprises a current sink connected to a ground rail. The circuit also includes first and second current-carrying branches of frequency-dividing circuitry operably connected to respective load resistors, which are connected to a power rail. A first switch element of the circuit is connected between the current sink and the first current-carrying branch and a second switch element of the circuit is connected between the current sink and the second current-carrying branch. The first and second switch elements may steer current sank by the current sink between the first and second current-carrying branches effective to alter a phase of a signal provided by the frequency division circuit.
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公开(公告)号：US09647638B2
公开(公告)日：2017-05-09
申请号：US14331685
申请日：2014-07-15
发明人： Mohammad Bagher Vahid Far , Cheng-Han Wang , Jesse Aaron Richmond , Thinh Cat Nguyen , Abbas Komijani , Yashar Rajavi , Alireza Khalili
CPC分类号： H03H11/0433 , H03H11/1252 , H04B1/109 , H04B1/525
摘要： A method and apparatus for minimizing transmit signal interference is provided. The method includes the steps of: receiving a signal and amplifying the received signal. The received signal is then mixed with an intermediate frequency signal to obtain a baseband modulated signal. The baseband modulated signal is first filtered in an RC filter. The resulting signal is then divided by a preselected amount and the first divided portion is sent to a main path of a biquad filter, which produces a first stage biquad filtered signal. The second portion of the divided signal is sent to an auxiliary path of the biquad filter, and produces a second filtered signal. The first and second signals are then recombined and sent to the second stage of the biquad filter, where further filtering takes place.
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公开(公告)号：US20170063383A1
公开(公告)日：2017-03-02
申请号：US14838204
申请日：2015-08-27
CPC分类号： H03L7/081 , H03L7/0807 , H03L7/099 , H04B7/0452 , H04W56/0015
摘要： This disclosure provides a device and method for synchronizing local oscillator (LO) chains. The method can include sampling first I-data and first Q-data to generate first sampled I-data and first sampled Q-data based on a sampling clock signal. The method can also include calibrating the sampling clock signal based on the first sampled I-data and the first sampled Q-data to generate a first calibrated sampling clock signal, the first calibrated sampling clock signal indicating an optimal sample position to sample the first I-data and the first Q-data. The method can also include synchronizing a phase of the first LO chain and a second LO chain based on the first calibrated sampling clock signal.
摘要翻译： 本公开提供了一种用于同步本地振荡器（LO）链的装置和方法。 该方法可以包括对第一I数据和第一Q数据进行采样，以便基于采样时钟信号产生第一采样的I数据和第一采样的Q数据。 该方法还可以包括基于第一采样的I数据和第一采样的Q数据来校准采样时钟信号以产生第一校准的采样时钟信号，第一校准采样时钟信号指示最佳采样位置以对第一I 数据和第一个Q数据。 该方法还可以包括基于第一校准采样时钟信号来同步第一LO链和第二LO链的相位。
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公开(公告)号：US20160028349A1
公开(公告)日：2016-01-28
申请号：US14338241
申请日：2014-07-22
发明人： Yashar Rajavi , Amirpouya Kavousian , Alireza Khalili , Mohammad Bagher Vahid Far , Abbas Komijani
IPC分类号： H03B5/36
CPC分类号： H03B5/364 , H03B5/06 , H03B5/36 , H03B2200/004 , H03B2200/0094
摘要： A differential crystal oscillator circuit, including: first and second output terminals; a cross-coupled oscillation unit including first and second transistors cross-coupled to the first and second output terminals; first and second metal-oxide semiconductor field-effect transistor (MOSFET) diodes, each MOSFET diode including a resistor connected between gate and drain terminals, wherein the first MOSFET diode couples to the first transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the first transistor, wherein the second MOSFET diode couples to the second transistor to provide low-impedance load at low frequencies and high-impedance load at higher frequencies to the second transistor; and a reference resonator coupled between the first and second output terminals to establish an oscillation frequency.
摘要翻译： 一种差分晶体振荡器电路，包括：第一和第二输出端子; 交叉耦合振荡单元，包括交叉耦合到第一和第二输出端的第一和第二晶体管; 第一和第二金属氧化物半导体场效应晶体管（MOSFET）二极管，每个MOSFET二极管包括连接在栅极和漏极端子之间的电阻器，其中第一MOSFET二极管耦合到第一晶体管以在低频和高电平下提供低阻抗负载 在第一晶体管的较高频率处的阻抗负载，其中所述第二MOSFET二极管耦合到所述第二晶体管，以在低频处提供低阻抗负载，并以较高频率向所述第二晶体管提供高阻抗负载; 以及耦合在第一和第二输出端子之间以建立振荡频率的参考谐振器。
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