公开(公告)号：US09349422B2

公开(公告)日：2016-05-24

申请号：US14687739

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC: G11C7/22 ,  G11C29/02 ,  G06F1/10

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算与子速率频率（例如，全速率频率的1/2，¼或⅛）相关联的子速率校准状态。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：US20240096387A1

公开(公告)日：2024-03-21

申请号：US18460413

申请日：2023-09-01

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/49 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US11211105B2

公开(公告)日：2021-12-28

申请号：US16987157

申请日：2020-08-06

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/02 ,  G11C8/12 ,  G11C5/06 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US10938605B2

公开(公告)日：2021-03-02

申请号：US16750924

申请日：2020-01-23

Applicant: Rambus Inc.

Inventor： Hae-Chang Lee ,  Brian S. Leibowitz ,  Jade M. Kizer ,  Thomas H. Greer ,  Akash Bansal

IPC: H04L25/03 ,  H04B1/12

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

公开(公告)号：US10770124B2

公开(公告)日：2020-09-08

申请号：US16222909

申请日：2018-12-17

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/02 ,  G11C8/12 ,  G11C5/06 ,  G11C8/18 ,  H01L25/065 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US10600497B2

公开(公告)日：2020-03-24

申请号：US15847559

申请日：2017-12-19

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Wayne F. Ellis ,  Akash Bansal

IPC: G11C5/04 ,  G11C29/50 ,  G06F13/16 ,  G01R23/02 ,  G11C7/22 ,  G11C29/02 ,  H03L1/02 ,  G11C8/18 ,  G06F11/16 ,  G06F1/12 ,  G06F1/08 ,  G01R23/15 ,  G01R35/00 ,  G11C7/04

Abstract: The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

公开(公告)号：US20190180813A1

公开(公告)日：2019-06-13

申请号：US16276338

申请日：2019-02-14

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G06F1/3234 ,  G11C29/02 ,  G11C7/02 ,  G11C11/4072 ,  G11C7/20

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20190139598A1

公开(公告)日：2019-05-09

申请号：US16235351

申请日：2018-12-28

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C11/4074 ,  G06F1/3234 ,  G11C29/02 ,  G11C7/02 ,  G11C11/4072 ,  G11C7/20

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10262718B2

公开(公告)日：2019-04-16

申请号：US15855535

申请日：2017-12-27

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C8/00 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a clock receiver to receive a clock signal and a plurality of mode registers to store parameter information associated with a plurality of operating clock frequencies of the clock signal. The plurality of clock frequencies include a first clock frequency and a second clock frequency. The memory device also includes a command interface to receive commands synchronously with respect to the clock signal. The command interface receives a command that instructs the DRAM device to change operation from the first clock frequency to the second clock frequency.

公开(公告)号：US10192598B2

公开(公告)日：2019-01-29

申请号：US15623261

申请日：2017-06-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06 ,  G11C8/12 ,  G11C5/02 ,  G11C8/18 ,  G11C5/04 ,  G11C7/10 ,  H01L23/00 ,  H01L25/065

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.