公开(公告)号：US10885971B2

公开(公告)日：2021-01-05

申请号：US16823122

申请日：2020-03-18

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ming Li

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/00

Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

公开(公告)号：US10719465B2

公开(公告)日：2020-07-21

申请号：US16601480

申请日：2019-10-14

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/36 ,  G06F13/362 ,  G11C16/26 ,  G11C16/10 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40 ,  H01L23/00 ,  H01L23/50 ,  G11C11/409 ,  G11C11/408 ,  H01L25/065 ,  H01L23/60 ,  H01L23/48 ,  H01L27/02

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US20200209911A1

公开(公告)日：2020-07-02

申请号：US16707957

申请日：2019-12-09

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC: G06F1/08 ,  G11C29/02 ,  G11C29/50 ,  H04L7/00 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14 ,  G06F1/12

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

公开(公告)号：US20200117627A1

公开(公告)日：2020-04-16

申请号：US16601480

申请日：2019-10-14

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  H01L27/02 ,  G11C16/26 ,  G11C16/10 ,  G11C14/00 ,  G11C11/4096 ,  G06F13/40 ,  H01L23/00 ,  H01L23/50 ,  G11C11/409 ,  G11C11/408 ,  H01L25/065 ,  H01L23/60 ,  H01L23/48

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US10522194B2

公开(公告)日：2019-12-31

申请号：US16148491

申请日：2018-10-01

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John W. Poulton

IPC: H04B15/00 ,  G11C5/14 ,  H04L25/02 ,  G06F13/40 ,  H04L1/20 ,  H04L25/08 ,  G06F11/07

Abstract: In a data transmission system, one or more signal supply voltages for generating the signaling voltage of a signal to be transmitted are generated in a first circuit and forwarded from the first circuit to a second circuit. The second circuit may use the forwarded signal supply voltages to generate another signal to be transmitted back from the second circuit to the first circuit, thereby obviating the need to generate signal supply voltages separately in the second circuit. The first circuit may also adjust the signal supply voltages based on the signal transmitted back from the second circuit to the first circuit. The data transmission system may employ a single-ended signaling system in which the signaling voltage is referenced to a reference voltage that is a power supply voltage such as ground, shared by the first circuit and the second circuit.

公开(公告)号：US10481973B2

公开(公告)日：2019-11-19

申请号：US15907210

申请日：2018-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent S. Haukness ,  John Eric Linstadt ,  Scott C. Best

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C5/04 ,  G11C29/04

Abstract: A memory module is disclosed. The memory module includes a substrate, and respective first, second and third memory devices. The first memory device is of a first type disposed on the substrate and has addressable storage locations. The second memory device is also of the first type, and includes storage cells dedicated to store failure address information associated with defective storage locations in the first memory device. The third memory device is of the first type and includes storage cells dedicated to substitute as storage locations for the defective storage locations.

公开(公告)号：US10388396B2

公开(公告)日：2019-08-20

申请号：US15506621

申请日：2015-08-17

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/00 ,  G11C29/44 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20190198085A1

公开(公告)日：2019-06-27

申请号：US16225109

申请日：2018-12-19

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: G11C11/4076 ,  G11C11/4091 ,  G11C7/22 ,  H04L7/033 ,  G11C7/10 ,  G06F1/10 ,  H03L7/081 ,  H03L7/07

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.

公开(公告)号：US20180364941A1

公开(公告)日：2018-12-20

申请号：US16010664

申请日：2018-06-18

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

CPC classification number: G06F3/0656 ,  G06F3/0626 ,  G06F3/0673 ,  G11C5/04 ,  G11C7/1006

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

公开(公告)号：US20180047437A1

公开(公告)日：2018-02-15

申请号：US15667706

申请日：2017-08-03

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Richard E. Warmke ,  David B. Roberts ,  Frank Lambrecht

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/4091

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4091 ,  G11C2207/107 ,  H03L7/07 ,  H03L7/0814 ,  H04L7/0337

Abstract: A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals.