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    Semiconductor device
    11.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10128200B2

    公开(公告)日：2018-11-13

    申请号：US15833289

    申请日：2017-12-06

    Applicant: Renesas Electronics Corporation

    Inventor： Kuniharu Muto ,  Ryo Kanda

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H02M7/5387 ,  H02P27/06

    Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09324862B2

    公开(公告)日：2016-04-26

    申请号：US14638996

    申请日：2015-03-04

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshinori Kaya ,  Yasushi Nakahara ,  Ryo Kanda ,  Tetsu Toda

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06

    CPC classification number: H01L29/0619 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835 ,  H03K19/017509

    Abstract: To prevent a current leak in an impurity region surrounding a transistor, in a region where a portion, of a second conductivity type region, extending from a first circuit region side toward a second circuit region side and an element separation film overlap each other in plan view, a field plate and conductive films are provided alternately from the first circuit region side toward the second circuit region side in plan view. Further, in this region, there is a decrease in the potential of the field plate and the potentials of the conductive films from the first circuit region toward the second circuit region. Further, at least one of the conductive films has a potential lower than the potential of the field plate adjacent to the conductive film on the second circuit region side in plan view. Further, this conductive film covers at least a part of the second conductivity type region without space in the extension direction of the second conductivity type region.

    Abstract translation: 为了防止在晶体管周围的杂质区域中的电流泄漏，在从第一电路区域侧朝向第二电路区域侧延伸的第二导电类型区域和元件分离膜的部分在计划中彼此重叠的区域中 在平面图中，从第一电路区域侧朝向第二电路区域侧交替地设置场板和导电膜。 此外，在该区域中，场板的电位和导电膜从第一电路区域朝向第二电路区域的电位降低。 此外，导电膜中的至少一个在平面图中具有低于第二电路区域侧上与导电膜相邻的场板的电位的电位。 此外，该导电膜覆盖第二导电类型区域的至少一部分，而在第二导电类型区域的延伸方向上没有空间。

    Semiconductor device and method of manufacturing the same
    13.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10651301B2

    公开(公告)日：2020-05-12

    申请号：US15980635

    申请日：2018-05-15

    Applicant: Renesas Electronics Corporation

    Inventor： Ryo Kanda ,  Hitoshi Matsuura

    IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40

    Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10573604B2

    公开(公告)日：2020-02-25

    申请号：US16151585

    申请日：2018-10-04

    Applicant: Renesas Electronics Corporation

    Inventor： Kuniharu Muto ,  Ryo Kanda

    IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H02M7/5387 ,  H02P27/06 ,  H02M7/00 ,  H02M1/00

    Abstract: A semiconductor device includes a first and second semiconductor chips, a resistive component, and a semiconductor chip including a first circuit coupled to electrodes on both ends of the resistive component. A sealing body has a first long side, a second side, a third short side, and a fourth short side. In a Y-direction, each of the first and second semiconductor chips is disposed at a position closer to the first side than to the second side, while the semiconductor chip is disposed at a position closer to the second side than to the first side. Also, in the Y-direction, the resistive component, the second semiconductor chips, and the first semiconductor chips are arranged in order of increasing distance from the third side toward the fourth side, while the semiconductor chip is disposed at a position closer to the third side than to the fourth side.

    Semiconductor Device
    17.
    发明申请
    Semiconductor Device 有权
    半导体器件

    公开(公告)号：US20150270390A1

    公开(公告)日：2015-09-24

    申请号：US14638996

    申请日：2015-03-04

    Applicant: Renesas Electronics Corporation

    Inventor： Yoshinori Kaya ,  Yasushi Nakahara ,  Ryo Kanda ,  Tetsu Toda

    IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40

    CPC classification number: H01L29/0619 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835 ,  H03K19/017509

    Abstract: To prevent a current leak in an impurity region surrounding a transistor, in a region where a portion, of a second conductivity type region, extending from a first circuit region side toward a second circuit region side and an element separation film overlap each other in plan view, a field plate and conductive films are provided alternately from the first circuit region side toward the second circuit region side in plan view. Further, in this region, there is a decrease in the potential of the field plate and the potentials of the conductive films from the first circuit region toward the second circuit region. Further, at least one of the conductive films has a potential lower than the potential of the field plate adjacent to the conductive film on the second circuit region side in plan view. Further, this conductive film covers at least a part of the second conductivity type region without space in the extension direction of the second conductivity type region.

    Abstract translation: 为了防止在晶体管周围的杂质区域中的电流泄漏，在从第一电路区域侧朝向第二电路区域侧延伸的第二导电类型区域和元件分离膜的部分在计划中彼此重叠的区域中 在平面图中，从第一电路区域侧朝向第二电路区域侧交替地设置场板和导电膜。 此外，在该区域中，场板的电位和导电膜从第一电路区域朝向第二电路区域的电位降低。 此外，导电膜中的至少一个在平面图中具有低于第二电路区域侧上与导电膜相邻的场板的电位的电位。 此外，该导电膜覆盖第二导电类型区域的至少一部分，而在第二导电类型区域的延伸方向上没有空间。

    Semiconductor device
    18.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09048213B2

    公开(公告)日：2015-06-02

    申请号：US14325003

    申请日：2014-07-07

    Applicant: Renesas Electronics Corporation

    Inventor： Ryo Kanda ,  Tetsu Toda ,  Yasushi Nakahara ,  Yoshinori Kaya

    IPC: H01L29/78 ,  H01L29/40 ,  H01L29/10 ,  H01L29/06 ,  H01L27/02

    CPC classification number: H01L27/0207 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

    Abstract: A field plate electrode is repetitively disposed in a folded manner or a spiral shape in a direction along an edge of a first circuit region. A coupling transistor couples a first circuit to a second circuit lower in supply voltage than the first circuit. A second conductivity type region is disposed around the coupling transistor. A part of the field plate electrode partially overlaps with the second conductivity type region. The field plate electrode is electrically coupled to a drain electrode of the coupling transistor at a portion located on the first circuit region side from a center thereof in a width direction of the separation region. A ground potential or a power potential of the second circuit is applied to the field plate electrode at a portion located on the second conductivity type region side from the center.

    Abstract translation: 场板电极在沿着第一电路区域的边缘的方向上以折叠方式或螺旋形状重复地布置。 耦合晶体管将第一电路耦合到电源电压低于第一电路的第二电路。 第二导电类型区域设置在耦合晶体管周围。 场板电极的一部分与第二导电类型区域部分重叠。 场平板电极在分离区域的宽度方向上的位于第一电路区域侧的部分的电极上耦合到耦合晶体管的漏电极。 第二电路的接地电位或功率电位在距中心的第二导电类型区域侧的部分施加到场板电极。

    Trench gate IGBT
    19.
    发明授权
    Trench gate IGBT 有权

    公开(公告)号：US10312357B2

    公开(公告)日：2019-06-04

    申请号：US15798218

    申请日：2017-10-30

    Applicant: Renesas Electronics Corporation

    Inventor： Ryo Kanda ,  Hitoshi Matsuura ,  Shuichi Kikuchi

    IPC: H01L29/739 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423

    Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

    Semiconductor device
    20.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10049968B2

    公开(公告)日：2018-08-14

    申请号：US15858493

    申请日：2017-12-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Yukihiro Sato ,  Akira Muto ,  Ryo Kanda ,  Takamitsu Kanazawa

    IPC: H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L27/06 ,  H01L29/739 ,  H01L25/075 ,  H02P27/06

    Abstract: To improve the reliability of a semiconductor device. A chip mounting portion TAB5 is arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP1 (LV) and a pad of a semiconductor chip CHP3 are electrically coupled by a wire W1a and a wire W1b through a relay lead RL1. Likewise, a gate electrode pad of a semiconductor chip CHP1 (LW) and the pad of the semiconductor chip CHP3 are electrically coupled by a wire W1c and a wire W1d through a relay lead RL2. At this time, the structures of parts of the relay leads RL1 and RL2, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LD1 and LD2 which function as external terminals.

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