公开(公告)号：US20150295053A1

公开(公告)日：2015-10-15

申请号：US14749274

申请日：2015-06-24

Applicant: RF Micro Devices, Inc.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/80 ,  H01L29/423 ,  H01L29/417

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Abstract translation: 公开了具有至少一种结构的场效应晶体管，其被配置为重新分布和/或减少栅极指末端的电场。 场效应晶体管的实施例包括基板，设置在基板上的有源区，与有源区接触的至少一个源极指，与有源区接触的至少一个漏极指，以及整流中的至少一个栅极指 与活动区域接触。 一个实施例具有至少一个门指的至少一端延伸到有源区的外部。 另一个实施例包括与所述至少一个源手指成一体的至少一个源极场板。 所述至少一个源极场板在所述至少一个栅极指状物上延伸，所述至少一个栅极指包括有源区域外部的部分。 任何一个实施例还可以包括倾斜门脚，以进一步改善高压操作。

公开(公告)号：US09136341B2

公开(公告)日：2015-09-15

申请号：US13795926

申请日：2013-03-12

Applicant: RF Micro Devices, Inc.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/812 ,  H01L29/66 ,  H01L29/40 ,  H01L29/778 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation.

Abstract translation: 公开了具有至少一种结构的场效应晶体管，其被配置为重新分布和/或减少栅极指末端的电场。 场效应晶体管的实施例包括基板，设置在基板上的有源区，与有源区接触的至少一个源极指，与有源区接触的至少一个漏极指，以及整流中的至少一个栅极指 与活动区域接触。 一个实施例具有至少一个门指的至少一端延伸到有源区的外部。 另一个实施例包括与所述至少一个源手指成一体的至少一个源极场板。 所述至少一个源极场板在所述至少一个栅极指状物上延伸，所述至少一个栅极指包括有源区域外部的部分。 任何一个实施例还可以包括倾斜门脚，以进一步改善高压操作。

公开(公告)号：US08988097B2

公开(公告)日：2015-03-24

申请号：US13914060

申请日：2013-06-10

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.

Abstract translation: 公开了半导体器件的晶片高压测试方法。 该方法包括将图案层添加到半导体器件的钝化层上，然后通过钝化层蚀刻通孔以暴露导电测试点。 半导体器件的测试开始于将导电测试点与测试装置的高电压测试探针接合，然后通过高压测试探针将高压测试序列施加到导电测试点。 半导体器件的测试通过将高电压测试探针与最后一个半导体器件分离，然后从半导体器件的钝化层去除图案化层来得出结论。

公开(公告)号：US20130280877A1

公开(公告)日：2013-10-24

申请号：US13795986

申请日：2013-03-12

Applicant: RF MICRO DEVICES, INC.

Inventor： Kevin Wesley Kobayashi ,  Haldane S. Henry ,  Andrew P. Ritenour

IPC: H01L29/66

CPC classification number: H01L29/402 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66477 ,  H01L29/7787 ,  H01L29/80 ,  H01L29/812

Abstract: Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation.

Abstract translation: 公开了制造具有至少一种结构的场效应晶体管的方法，该结构被配置为重新分布和/或减少栅极指末端的电场。 这些方法提供场效应晶体管，其各自包括衬底，设置在衬底上的有源区，与有源区接触的至少一个源极指，与有源区接触的至少一个漏极指，以及至少一个栅极指 与活性区域整流接触。 一个实施例具有至少一个门指的至少一端延伸到有源区的外部。 至少一种方法包括以预定斜率将至少一个栅极通道蚀刻到钝化层中，该斜率减小栅极边缘处的电场。 其他方法包括用于制造倾斜门脚，圆端和/或倒角端的步骤，以进一步改善高压操作。

公开(公告)号：US20150357457A1

公开(公告)日：2015-12-10

申请号：US14731736

申请日：2015-06-05

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/778 ,  H01L29/812 ,  H01L29/49 ,  H01L29/51 ,  H01L29/20 ,  H01L29/47

CPC classification number: H01L29/517 ,  H01L21/28264 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/42364 ,  H01L29/475 ,  H01L29/4958 ,  H01L29/518 ,  H01L29/778 ,  H01L29/78 ,  H01L29/812

Abstract: A Schottky gated transistor having reduced gate leakage current is disclosed. The Schottky gated transistor includes a substrate and a plurality of epitaxial layers disposed on the substrate. Further included is a gate contact having an interfacial layer disposed on a surface of the plurality of epitaxial layers and having a thickness that is between about 5 Angstroms (Å) and 40 Å. The interfacial layer can be made up of non-native materials in contrast to a native insulator such as silicon dioxide (SiO2) that is used as an insulating gate layer with silicon-based power transistors. The Schottky gated transistor further includes at least one metal layer disposed over the interfacial layer. A source contact and a drain contact are disposed on the surface of the plurality of epitaxial layers, wherein the source contact and the drain contact are spaced apart from the gate contact and each other.

Abstract translation: 公开了一种具有降低的栅极漏电流的肖特基门控晶体管。 肖特基门控晶体管包括衬底和设置在衬底上的多个外延层。 进一步包括的栅极接触件具有设置在多个外延层的表面上并具有介于约5埃（埃）和40埃之间的厚度的界面层。 与天然绝缘体（例如用作具有硅基功率晶体管的绝缘栅极层的二氧化硅（SiO 2））相比，界面层可以由非天然材料构成。 肖特基门控晶体管还包括设置在界面层上的至少一个金属层。 源极触点和漏极触点设置在多个外延层的表面上，其中源极触点和漏极触点与栅极触点和彼此间隔开。

公开(公告)号：US09202874B2

公开(公告)日：2015-12-01

申请号：US13957698

申请日：2013-08-02

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/20 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/42316 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/778

Abstract: A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.

Abstract translation: 公开了一种具有基于漏电流的过电压保护的氮化镓（GaN）器件。 GaN器件包括设置在半导体衬底上的漏极和源极。 GaN器件还包括半导体衬底内的第一沟道区域和漏极与源极之间。 GaN器件还包括半导体衬底内的第二沟道区域和漏极与源极之间。 第二通道区域具有大于第一通道区域的DIBL的增强的漏极引发屏障降低（DIBL）。 结果，一旦大量漏极电流开始流过第二沟道区域，漏极电压将被安全地夹在破坏性击穿电压之下。

公开(公告)号：US09142620B2

公开(公告)日：2015-09-22

申请号：US13910202

申请日：2013-06-05

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour ,  Paul Partyka

IPC: H01L29/15 ,  H01L29/66 ,  H01L21/338 ,  H01L21/20 ,  H01L29/20 ,  H01L21/02 ,  H01L29/417 ,  H01L23/36

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L23/36 ,  H01L29/4175 ,  H01L2224/16 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/00

Abstract: The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.

Abstract translation: 本公开提供了功率器件和功率器件封装。 通常，本公开的功率器件包括管芯背面和管芯前端。 具有设置在其上的外延层的半绝缘基板夹在模具背面和模具前侧之间。 模具前端的垫片与模具背面耦合，图案化的背衬设置在通过半绝缘衬底和外延层从模具背面到模具前端的通孔内。

公开(公告)号：US09129802B2

公开(公告)日：2015-09-08

申请号：US13973482

申请日：2013-08-22

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L21/00 ,  H01L27/02 ,  H01L29/417 ,  H01L29/778 ,  H01L29/861 ,  H01L29/20

CPC classification number: H01L27/0248 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41775 ,  H01L29/778 ,  H01L29/861

Abstract: A lateral semiconductor device having a vertical region for providing a protective avalanche breakdown (PAB) is disclosed. The lateral semiconductor device has a lateral structure that includes a conductive substrate, semi-insulating layer(s) disposed on the conductive substrate, device layer(s) disposed on the semi-insulating layer(s), along with a source electrode and a drain electrode disposed on the device layer(s). The vertical region is separated from the source electrode by a lateral region wherein the vertical region has a relatively lower breakdown voltage level than a relatively higher breakdown voltage level of the lateral region for providing the PAB within the vertical region to prevent a potentially damaging breakdown of the lateral region. The vertical region is structured to be more rugged than the lateral region and thus will not be damaged by a PAB event.

Abstract translation: 公开了具有用于提供保护性雪崩击穿（PAB）的垂直区域的横向半导体器件。 横向半导体器件具有横向结构，其包括导电衬底，设置在导电衬底上的半绝缘层，设置在半绝缘层上的器件层以及源电极和 漏电极设置在器件层上。 垂直区域通过横向区域与源极分离，其中垂直区域具有比用于在垂直区域内提供PAB的相对较高的击穿电压电平相对较低的击穿电压电平，以防止潜在的破坏性破坏 侧面区域。 垂直区域被构造成比横向区域更坚固，因此不会被PAB事件损坏。

公开(公告)号：US20140057372A1

公开(公告)日：2014-02-27

申请号：US13914060

申请日：2013-06-10

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for wafer high voltage testing of semiconductor devices is disclosed. The method involves adding a patterning layer onto a passivation layer of the semiconductor devices and then etching vias through the passivation layer to expose conductive test points. Testing of the semiconductor devices begins with engaging the conductive test points with high voltage test probes of a testing apparatus and then applying a high voltage test sequence to the conductive test points via the high voltage test probes. The testing of the semiconductor devices concludes by disengaging the high voltage test probes from a last one of the semiconductor devices and then removing the patterning layer from the passivation layer of the semiconductor devices.

Abstract translation: 公开了半导体器件的晶片高压测试方法。 该方法包括将图案层添加到半导体器件的钝化层上，然后通过钝化层蚀刻通孔以暴露导电测试点。 半导体器件的测试开始于将导电测试点与测试装置的高电压测试探针接合，然后通过高压测试探针将高压测试序列施加到导电测试点。 半导体器件的测试通过将高电压测试探针与最后一个半导体器件分离，然后从半导体器件的钝化层去除图案化层来得出结论。

公开(公告)号：US20140054601A1

公开(公告)日：2014-02-27

申请号：US13957698

申请日：2013-08-02

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L29/42316 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/778

Abstract: A gallium nitride (GaN) device with leakage current-based over-voltage protection is disclosed. The GaN device includes a drain and a source disposed on a semiconductor substrate. The GaN device also includes a first channel region within the semiconductor substrate and between the drain and the source. The GaN device further includes a second channel region within the semiconductor substrate and between the drain and the source. The second channel region has an enhanced drain induced barrier lowering (DIBL) that is greater than the DIBL of the first channel region. As a result, a drain voltage will be safely clamped below a destructive breakdown voltage once a substantial drain current begins to flow through the second channel region.

Abstract translation: 公开了一种具有基于漏电流的过电压保护的氮化镓（GaN）器件。 GaN器件包括设置在半导体衬底上的漏极和源极。 GaN器件还包括半导体衬底内的第一沟道区域和漏极与源极之间。 GaN器件还包括半导体衬底内的第二沟道区域和漏极与源极之间。 第二通道区域具有大于第一通道区域的DIBL的增强的漏极引发屏障降低（DIBL）。 结果，一旦大量漏极电流开始流过第二沟道区域，漏极电压将被安全地夹在破坏性击穿电压之下。