公开(公告)号：US20080076076A1

公开(公告)日：2008-03-27

申请号：US11534342

申请日：2006-09-22

申请人： Yaw Samuel Obeng ,  Yu-Tai Lee ,  Rajesh Khamankar ,  April Gurba ,  Brian Kirkpatrick ,  Ajith Varghese

发明人： Yaw Samuel Obeng ,  Yu-Tai Lee ,  Rajesh Khamankar ,  April Gurba ,  Brian Kirkpatrick ,  Ajith Varghese

IPC分类号： G03F7/26

CPC分类号： H01L21/0273 ,  G03F7/423 ,  G03F7/427

摘要： In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.

摘要翻译： 在一个实施例中，一种制造集成电路的方法包括在衬底上形成电路层，在电路层上形成抗蚀剂层，并对抗蚀剂层进行包括将抗蚀剂层暴露于有机洗涤物的返工工艺。 在另一个实施例中，制造集成电路的方法包括在衬底上形成电路层，在电路层上形成起动层，并对抗蚀剂层进行返工处理。 返修过程包括将基底暴露于温和的等离子体灰中以基本上去除抗蚀剂层的部分，但留下引发层。

公开(公告)号：US07339240B2

公开(公告)日：2008-03-04

申请号：US11343680

申请日：2006-01-31

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L29/76

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片 在暴露的氮化高压栅极介电层上的促进剂残留物。 该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

公开(公告)号：US07049242B2

公开(公告)日：2006-05-23

申请号：US10752886

申请日：2004-01-06

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L21/302

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片 在暴露的氮化高压栅极介电层上的促进剂残留物。 该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

公开(公告)号：US20070128806A1

公开(公告)日：2007-06-07

申请号：US11670192

申请日：2007-02-01

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

IPC分类号： H01L21/336

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

摘要： A silicon nitrate layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

摘要翻译： 在晶体管栅极（40）和源极和漏极区域（70）之上形成硝酸氧化物层（110）。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

公开(公告)号：US20050245012A1

公开(公告)日：2005-11-03

申请号：US10833419

申请日：2004-04-28

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

IPC分类号： H01L21/336 ,  H01L23/58 ,  H01L29/78

CPC分类号： H01L29/7842 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7843 ,  Y10S438/954

摘要： A silicon nitride layer (110) is formed over a transistor gate (40) and source and drain regions (70). The as-formed silicon nitride layer (110) comprises a first tensile stress and a high hydrogen concentration. The as-formed silicon nitride layer (110) is thermally annealed converting the first tensile stress into a second tensile stress that is larger than the first tensile stress. Following the thermal anneal, the hydrogen concentration in the silicon nitride layer (110) is greater than 12 atomic percent.

摘要翻译： 氮化硅层（110）形成在晶体管栅极（40）和源极和漏极区域（70）之上。 所形成的氮化硅层（110）包括第一拉伸应力和高氢浓度。 将所形成的氮化硅层（110）进行热退火，将第一拉伸应力转换成大于第一拉伸应力的第二拉伸应力。 在热退火之后，氮化硅层（110）中的氢浓度大于12原子％。

公开(公告)号：US20050233514A1

公开(公告)日：2005-10-20

申请号：US10827692

申请日：2004-04-19

申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas Grider

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8238

CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  Y10S438/938

摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

摘要翻译： 提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130）以在NMOS晶体管的全部或一部分中施加拉伸应力以改善载流子迁移率。 氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。 随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

公开(公告)号：US06730566B2

公开(公告)日：2004-05-04

申请号：US10264729

申请日：2002-10-04

申请人： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

发明人： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  Y10S438/92

摘要： A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.

摘要翻译： 提供了用于高压晶体管器件的非热氮化栅极形成的方法。 非热氮化栅极形成可用于双厚度栅极电介质结构的形成。 非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。 栅极电介质层的氮化破坏了栅极电介质层的表面。 通过相对较低温度的再氧化工艺去除栅介电层的受损表面。 低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。

公开(公告)号：US06632747B2

公开(公告)日：2003-10-14

申请号：US09885600

申请日：2001-06-20

申请人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

发明人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

IPC分类号： H01L2131

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.

摘要翻译： 本发明的一个实施例是通过提供具有半导体表面的衬底来形成超薄电介质层的方法; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火该层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自一组四种再氧化技术：连续 在H 2和N 2（优选小于20％H 2）的混合物中进行退火，然后将O 2和N 2（优选小于20％的O 2）的混合物进行退火;通过尖峰状温度升高（优选小于20％ （优选为N 2 / O 2或N 2 O / H 2）;通过在减压下的氨中快速热加热（优选在600至1000℃下，对于 5至60秒）;在800至1050℃下在氧化剂/氢气混合物（优选N 2 O与1％H 2）中退火5至60秒。

公开(公告)号：US06780719B2

公开(公告)日：2004-08-24

申请号：US09885744

申请日：2001-06-20

申请人： Hiroaki Niimi ,  Rajesh Khamankar ,  James J. Chambers ,  Sunil Hattangady ,  Antonio L. P. Rotondaro

发明人： Hiroaki Niimi ,  Rajesh Khamankar ,  James J. Chambers ,  Sunil Hattangady ,  Antonio L. P. Rotondaro

IPC分类号： H01L21336

CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% O2); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.

摘要翻译： 本发明的一个实施例是形成超薄介电层的方法，该方法包括以下步骤：提供具有半导体表面的基板; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自四种再氧化技术：在H2和N2的混合物中连续退火 （优选小于20％H 2），然后是O 2和N 2（优选小于20％O 2）的混合物;通过尖峰状升温（优选在1000至1150℃下优选小于1秒）在氮气中退火 （优选为N 2 / O 2或N 2 O / H 2）;通过在减压的氨中快速热加热（优选在600至1000℃下5至60秒）进行退火;在氧化剂/氢气混合物（优选N 2 O 1％H 2）在800至1050℃下进行5至60秒。

公开(公告)号：US20070105294A1

公开(公告)日：2007-05-10

申请号：US11268040

申请日：2005-11-07

申请人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

发明人： Srinivasan Chakravarthi ,  Pr Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas Grider

IPC分类号： H01L21/8234

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。