公开(公告)号：US20080076076A1

公开(公告)日：2008-03-27

申请号：US11534342

申请日：2006-09-22

申请人： Yaw Samuel Obeng ,  Yu-Tai Lee ,  Rajesh Khamankar ,  April Gurba ,  Brian Kirkpatrick ,  Ajith Varghese

发明人： Yaw Samuel Obeng ,  Yu-Tai Lee ,  Rajesh Khamankar ,  April Gurba ,  Brian Kirkpatrick ,  Ajith Varghese

IPC分类号： G03F7/26

CPC分类号： H01L21/0273 ,  G03F7/423 ,  G03F7/427

摘要： In one embodiment, a method of manufacturing an integrated circuit that comprises forming a circuit layer over a substrate, forming a resist layer on the circuit layer, and subjecting the resist layer to a rework process that includes exposing the resist layer to an organic wash. In another embodiment, the method of manufacturing an integrated circuit comprises forming a circuit layer over a substrate, forming a priming layer on the circuit layer, and subjecting the resist layer to the rework process. The reworking process includes exposing the substrate to a mild plasma ash to substantially remove portions of the resist layer but leave the priming layer.

摘要翻译： 在一个实施例中，一种制造集成电路的方法包括在衬底上形成电路层，在电路层上形成抗蚀剂层，并对抗蚀剂层进行包括将抗蚀剂层暴露于有机洗涤物的返工工艺。 在另一个实施例中，制造集成电路的方法包括在衬底上形成电路层，在电路层上形成起动层，并对抗蚀剂层进行返工处理。 返修过程包括将基底暴露于温和的等离子体灰中以基本上去除抗蚀剂层的部分，但留下引发层。

公开(公告)号：US20060183337A1

公开(公告)日：2006-08-17

申请号：US11343680

申请日：2006-01-31

申请人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

发明人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC分类号： H01L21/302 ,  C23F1/00 ,  B44C1/22

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

公开(公告)号：US20060084229A1

公开(公告)日：2006-04-20

申请号：US11292883

申请日：2005-12-02

申请人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

发明人： Brian Kirkpatrick ,  Rajesh Khamankar ,  Malcolm Bevan ,  April Gurba ,  Husam Alshareef ,  Clinton Montgomery ,  Mark Somervell

IPC分类号： H01L21/8234

CPC分类号： H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

公开(公告)号：US20050156286A1

公开(公告)日：2005-07-21

申请号：US11038545

申请日：2005-01-18

申请人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477 ,  H01L23/58

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US20060175294A1

公开(公告)日：2006-08-10

申请号：US11327903

申请日：2006-01-09

申请人： Joe Tran ,  Chad Kaneshige ,  Brian Kirkpatrick

发明人： Joe Tran ,  Chad Kaneshige ,  Brian Kirkpatrick

IPC分类号： C03C15/00 ,  H01L21/306 ,  H01L21/00 ,  C23F1/00

CPC分类号： B24B37/26 ,  H01L21/31053

摘要： A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

摘要翻译： 描述了通过化学机械抛光工艺从半导体晶片的表面去除材料的方法。 该方法使用其上形成有线图案的抛光垫。 该图案包括有序间隔的开槽面积和无凹槽的区域。 该方法结合了晶片的表面形貌，待去除材料的性质和抛光垫表面上的可用凹槽图案的信息，以产生半导体晶片的部分驻留时间花费的处理配方 在化学机械抛光过程中在抛光垫的开槽和未开槽区域预先确定。

公开(公告)号：US20060266383A1

公开(公告)日：2006-11-30

申请号：US11141532

申请日：2005-05-31

申请人： Joe Tran ,  Brian Kirkpatrick ,  Alfred Griffin

发明人： Joe Tran ,  Brian Kirkpatrick ,  Alfred Griffin

IPC分类号： B08B3/04

CPC分类号： H01L21/6708

摘要： A system (500) for removing wafer edge residue from a target wafer (508) is disclosed. A wafer holding mechanism (502) holds and optionally rotates the target wafer (508). A solution dispenser (504) applies a residue remover solution (506) to an edge/beveled surface at an outer edge of the wafer (508) by directing the residue remover solution (506) to a target location on the wafer (508) causing the residue remover solution (506) to come in contact with the edge surface of the wafer (508). The residue remover solution (506) contains an etch component that etches semiconductor material from the edge surface of the wafer (508). As a result, underlying semiconductor material below strongly adhered residue is removed thereby dislodging the strongly adhered residue.

摘要翻译： 公开了一种用于从目标晶片（508）去除晶片边缘残余物的系统（500）。 晶片保持机构（502）保持并任选地旋转目标晶片（508）。 溶液分配器（504）通过将剩余物去除剂溶液（506）引导到晶片（508）上的目标位置，将残留物去除剂溶液（506）施加到晶片（508）的外边缘处的边缘/斜面，从而 残留物去除剂溶液（506）与晶片（508）的边缘表面接触。 残留物去除剂溶液（506）含有从晶片（508）的边缘表面蚀刻半导体材料的蚀刻部件。 结果，除去强烈附着的残留物以下的下面的半导体材料，从而移除强粘附的残留物。

公开(公告)号：US20050208732A1

公开(公告)日：2005-09-22

申请号：US11142483

申请日：2005-06-01

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US20050090115A1

公开(公告)日：2005-04-28

申请号：US10692609

申请日：2003-10-24

申请人： Brian Kirkpatrick ,  Clint Montgomery ,  Brian Trentman ,  Randall Pak

发明人： Brian Kirkpatrick ,  Clint Montgomery ,  Brian Trentman ,  Randall Pak

IPC分类号： B08B7/00 ,  H01L21/02 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/76 ,  H01L21/762 ,  H01L21/302

CPC分类号： H01L21/02054 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/76224

摘要： The present invention provides a process of manufacturing a semiconductor device that comprises a process of manufacturing a semiconductor device that includes plasma etching 250 through a patterned hardmask layer 210 located over a semiconductor substrate 225 wherein the plasma etching forms a modified layer 210a on the hardmask layer 210, and removing at least a substantial portion of the modified layer 210a by exposing the modified layer 210a to a post plasma clean process.

公开(公告)号：US20050062127A1

公开(公告)日：2005-03-24

申请号：US10691843

申请日：2003-10-23

申请人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

发明人： Zhihao Chen ,  Freidoon Mehrad ,  Brian Kirkpatrick ,  Jeff White ,  Edmund Russell ,  Jon Holt ,  Jason Mehigan

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L29/00

CPC分类号： H01L21/02126 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/31662 ,  H01L21/76235

摘要： A trench structure in a wafer of semiconductor material and the method of forming the trench structure are described. The trench structure is formed on a semiconductor wafer that has a top surface of slow oxidization rate—slower than that of other major crystallographic planes of the semiconductor material. The trench is etched into the semiconductor wafer. The trench has substantially vertical trench-sidewalls near the top surface, the vertical trench-sidewalls near the top surface containing crystallographic plane that oxidizes at a rate comparable to that of the top surface. An insulating layer is grown on the top surface and on the trench-sidewalls and on corners where sidewall surfaces approach the top surface, the insulating layer at the corners being substantially thicker than at the sidewall adjacent to the corners. The difference in the oxide thickness is due to the faster oxidizing planes exposed at the corners. Finally, the trench is filled with a dielectric material.

公开(公告)号：US20070050077A1

公开(公告)日：2007-03-01

申请号：US11551793

申请日：2006-10-23

申请人： Joe Tran ,  Chad Kaneshige ,  Brian Kirkpatrick

发明人： Joe Tran ,  Chad Kaneshige ,  Brian Kirkpatrick

IPC分类号： G06F19/00

CPC分类号： B24B37/26 ,  H01L21/31053

摘要： A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.

摘要翻译： 描述了通过化学机械抛光工艺从半导体晶片的表面去除材料的方法。 该方法使用其上形成有线图案的抛光垫。 该图案包括有序间隔的开槽面积和无凹槽的区域。 该方法结合了晶片的表面形貌，待去除材料的性质和抛光垫表面上的可用凹槽图案的信息，以产生半导体晶片的部分驻留时间花费的处理配方 在化学机械抛光过程中在抛光垫的开槽和未开槽区域预先确定。