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    RESISTANCE MEMORY CELL
    11.
    发明申请
    RESISTANCE MEMORY CELL 有权
    电阻存储单元

    公开(公告)号：US20160240249A1

    公开(公告)日：2016-08-18

    申请号：US15040921

    申请日：2016-02-10

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Gary Bela Bronner

    IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

    CPC classification number: G11C13/004 ,  G11C13/00 ,  G11C13/0011 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0052 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2418 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143

    Abstract: A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access device affects the current-voltage characteristic of the resistance memory cell. The resistance memory additionally includes a circuit to apply across the resistance memory cell a set pulse having a set polarity to set the resistance memory cell to a low-resistance state that is retained after application of the set pulse, a reset pulse having a reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained after application of the reset pulse, and a read pulse of the reset polarity and smaller in magnitude than the reset pulse to determine the resistance state of the resistance memory cell without changing the resistance state of the resistance memory cell.

    Abstract translation: 电阻存储器包括具有电阻存储元件和串联的两端存取装置的电阻存储单元。 双端子存取装置影响电阻存储单元的电流 - 电压特性。 电阻存储器还包括电路，跨越电阻存储单元施加具有设定极性的设定脉冲，以将电阻存储单元设置为在施加设置脉冲之后保持的低电阻状态，具有复位极性的复位脉冲 与设定的极性相反，将电阻存储单元复位到施加复位脉冲之后保持的高电阻状态，以及复位极性的读取脉冲和幅度比复位脉冲更小以确定电阻状态 的电阻存储单元，而不改变电阻存储单元的电阻状态。

    DYNAMIC MEMORY RANK CONFIGURATION
    12.
    发明申请
    DYNAMIC MEMORY RANK CONFIGURATION 审中-公开
    动态记忆排名配置

    公开(公告)号：US20160071608A1

    公开(公告)日：2016-03-10

    申请号：US14940084

    申请日：2015-11-12

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent S. Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0035 ,  G11C16/06 ,  H01L21/324

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Abstract translation: 存储器控制组件内的控制逻辑在相应的时间向存储器模块输出第一和第二存储器读取命令，存储器模块具有置于其上的存储器组件。 存储器控制组件内的接口电路响应于第一存储器读取命令分别经由第一多个数据路径从第一多个存储器组件同时接收第一读取数据，并且从第二个多个 所述存储器组件分别响应于所述第二存储器读取命令经由第二多个数据路径，所述第一多个存储器组件包括不包括在所述第二多个存储器组件中的至少一个存储器组件，反之亦然。

    System and Method for Writing Data to an RRAM Cell
    14.
    发明申请
    System and Method for Writing Data to an RRAM Cell 审中-公开
    将数据写入RRAM单元的系统和方法

    公开(公告)号：US20130250657A1

    公开(公告)日：2013-09-26

    申请号：US13789543

    申请日：2013-03-07

    Applicant: Rambus Inc.

    Inventor： Brent Steven Haukness ,  Mark D. Kellam ,  Gary B. Bronner ,  Craig Hampel

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C13/0011 ,  G11C13/0064 ,  G11C2013/0066 ,  G11C2213/79

    Abstract: A resistive RAM device includes a bit line, a word line, an RRAM cell coupled to the word line and to the bit line, a write driver and a disable circuit. The write driver is coupled to the bit line. The disable circuit stops a write operation performed by the write driver on a respective RRAM cell when a predefined condition on the bit line is achieved. The predefined condition depends on a mode of operation of the RRAM cell.

    Abstract translation: 电阻RAM装置包括位线，字线，耦合到字线和位线的RRAM单元，写驱动器和禁止电路。 写驱动器耦合到位线。 当实现位线上的预定义条件时，禁止电路在相应的RRAM单元上停止由写入驱动器执行的写入操作。 预定义条件取决于RRAM单元的操作模式。

    Bus distribution using multiwavelength multiplexing
    15.
    发明授权
    Bus distribution using multiwavelength multiplexing 有权

    公开(公告)号：US12292601B2

    公开(公告)日：2025-05-06

    申请号：US17963065

    申请日：2022-10-10

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Dongyun Lee ,  Thomas Vogelsang ,  Steven C. Woo

    IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

    Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.

    DYNAMIC MEMORY RANK CONFIGURATION
    17.
    发明申请
    DYNAMIC MEMORY RANK CONFIGURATION 有权

    公开(公告)号：US20220238159A1

    公开(公告)日：2022-07-28

    申请号：US17567401

    申请日：2022-01-03

    Applicant: Rambus Inc.

    Inventor： Gary B. Bronner ,  Brent Steven Haukness ,  Mark A. Horowitz ,  Mark D. Kellam ,  Fariborz Assaderaghi

    IPC: G11C16/06 ,  G11C13/00 ,  G11C16/26

    Abstract: Control logic within a memory control component outputs first and second memory read commands to a memory module at respective times, the memory module having memory components disposed thereon. Interface circuitry within the memory control component receives first read data concurrently from a first plurality of the memory components via a first plurality of data paths, respectively, in response to the first memory read command, and receives second read data concurrently from a second plurality of the memory components via a second plurality of data paths, respectively, in response to the second memory read command, the first plurality of the memory components including at least one memory component not included in the second plurality of the memory components and vice-versa.

    Pulse control for nonvolatile memory
    18.
    发明授权
    Pulse control for nonvolatile memory 有权
    非易失性存储器的脉冲控制

    公开(公告)号：US09177655B2

    公开(公告)日：2015-11-03

    申请号：US14145962

    申请日：2014-01-01

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  Brent Steven Haukness ,  Gary B. Bronner ,  Kevin Donnelly

    IPC: G11C16/12 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3459

    Abstract: A nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about 20 nanoseconds, while a “rest period” between pulses can be on the order of about a hundred nanoseconds or greater. Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of 50 nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

    Abstract translation: 非易失性存储器件，其使用脉冲控制和休止期来减轻缺陷前体的形成。 第一实施例使用脉冲位线控制，其中当希望改变相关联的存储器单元中的状态时，存储器单元通道与参考电压之间的耦合是脉冲的。 每个脉冲可以选择为小于约20纳秒，而脉冲之间的“休止期”可以在大约一百纳秒或更大的数量级。 由于使用位线控制，所以可以启用非常短的上升时间，可以产生50纳秒或更短的脉冲持续时间。 在其他实施例中，这些方法还可以更一般地应用于其它导体（例如，字线或衬底阱，用于编程或擦除操作）; 也可以使用分段字线或位线，以最小化RC负载并且实现足够短的上升时间以使脉冲稳健。

    Vertical interconnects with variable pitch for scalable escape routing
    20.
    发明授权
    Vertical interconnects with variable pitch for scalable escape routing 有权

    公开(公告)号：US12237255B2

    公开(公告)日：2025-02-25

    申请号：US17499712

    申请日：2021-10-12

    Applicant: Rambus Inc.

    Inventor： Mark D. Kellam ,  John Eric Linstadt

    IPC: H01L23/498

    Abstract: The embodiments are directed to technologies for variable pitch vertical interconnect design for scalable escape routing in semiconductor devices. One semiconductor device includes a circuit die, and an array of circuit die interconnects located on the circuit die. The array includes a first triangular octant of interconnects that are organized in rows and columns, each column incrementing its number of interconnects from a first side of the first triangular octant to a second side of the first triangular octant. A pitch size between the columns increases in a first repeating pattern from the first side to the second side.

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