公开(公告)号：US10756115B2

公开(公告)日：2020-08-25

申请号：US16670918

申请日：2019-10-31

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L21/8234 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8238

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US10510775B2

公开(公告)日：2019-12-17

申请号：US15695410

申请日：2017-09-05

Applicant: Renesas Electronics Corporation

Inventor： Takaaki Tsunomura ,  Yoshiki Yamamoto ,  Masaaki Shinohara ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/417 ,  H01L21/8238

Abstract: On a semiconductor substrate having an SOI region and a bulk silicon region formed on its upper surface, epitaxial layers are formed in source and drain regions of a MOSFET formed in the SOI region, and no epitaxial layer is formed in source and drain regions of a MOSFET formed in the bulk silicon region. By covering the end portions of the epitaxial layers with silicon nitride films, even when diffusion layers are formed by implanting ions from above the epitaxial layers, it is possible to prevent the impurity ions from being implanted down to a lower surface of a silicon layer.

公开(公告)号：US09966452B2

公开(公告)日：2018-05-08

申请号：US14864781

申请日：2015-09-24

Applicant: Renesas Electronics Corporation

Inventor： Hidekazu Oda

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/66 ,  H01L29/36 ,  H01L29/16 ,  H01L29/06 ,  H01L21/324 ,  H01L21/265 ,  H01L29/167 ,  H01L29/78 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66068 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/76251 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/36 ,  H01L29/78 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78654 ,  H01L29/78687

Abstract: A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide.

公开(公告)号：US09508598B2

公开(公告)日：2016-11-29

申请号：US14739065

申请日：2015-06-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidekazu Oda

IPC: H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/6656 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

Abstract translation: 为了提高具有完全耗尽的SOI晶体管的半导体器件的可靠性和性能，而形成在栅电极的侧壁上的偏移间隔物的宽度被配置为大于或等于半导体层的厚度并且更小 除了半导体层的厚度和绝缘膜的厚度的总和的厚度以外，杂质被离子注入到未被栅电极和偏移间隔物覆盖的半导体层中。 因此，通过离子注入杂质形成的延伸层不会从低于栅电极的端部的位置进入沟道。

公开(公告)号：US20140322878A1

公开(公告)日：2014-10-30

申请号：US14325570

申请日：2014-07-08

Applicant: Renesas Electronics Corporation

Inventor： Hirokazu SAYAMA ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L27/108 ,  H01L27/11

CPC classification number: H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

Abstract translation: 用于形成nMOS晶体管的非绝缘硅栅极绝缘膜和栅电极设置在硅衬底上。 使用栅电极作为掩模，注入具有较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此栅极电极 非晶化 随后，提供氧化硅膜以覆盖栅电极，其温度小于栅电极发生再结晶的温度。 此后，在约1000℃的温度下进行热处理，由此在栅极上施加高的压缩残余应力，并且对栅电极下方的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US08642418B2

公开(公告)日：2014-02-04

申请号：US13964849

申请日：2013-08-12

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu Ota ,  Hirokazu Sayama ,  Hidekazu Oda

IPC: H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20130330890A1

公开(公告)日：2013-12-12

申请号：US13964849

申请日：2013-08-12

Applicant: Renesas Electronics Corporation

Inventor： Kazunobu OTA ,  Hirokazu Sayama ,  Hidekazu Oda

IPC: H01L21/8238

CPC classification number: H01L29/42368 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/28017 ,  H01L21/28158 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/517 ,  H01L29/518

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

公开(公告)号：US20130175611A1

公开(公告)日：2013-07-11

申请号：US13735857

申请日：2013-01-07

Applicant: Renesas Electronics Corporation

Inventor： Hirofumi Shinohara ,  Hiromasa Yoshimori ,  Toshiaki Iwamatsu ,  Hidekazu Oda

IPC: H01L21/02 ,  H01L27/088

CPC classification number: H01L21/02697 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/0924

Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.

Abstract translation: 降低了形成低电压场效应晶体管的区域的顶视图中的区域，并且降低了形成高电压场效应晶体管的区域的顶视图中的区域。 形成低电压场效应晶体管（第一nMIS和第一pMIS）的有源区域由从元件隔离部分的表面突出的半导体衬底的第一凸部和高电场电场效应晶体管的有源区域构成， 形成电压场效应晶体管（第二nMIS和第二pMIS）由半导体衬底的从元件隔离部分的表面突出的第二凸部和形成在半导体衬底中的沟槽部分构成。

公开(公告)号：US12198987B2

公开(公告)日：2025-01-14

申请号：US17353079

申请日：2021-06-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/3215 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H10B10/00 ,  H10B12/00

Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.

公开(公告)号：US10050122B2

公开(公告)日：2018-08-14

申请号：US15299216

申请日：2016-10-20

Applicant: Renesas Electronics Corporation

Inventor： Hidekazu Oda

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/786 ,  H01L27/12 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L21/822

Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.