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11.发明授权Apparatus and method to track command signal occurrence for DRAM data transfer 失效用于跟踪DRAM数据传输的命令信号发生的装置和方法公开(公告)号：US06976121B2
公开(公告)日：2005-12-13
申请号：US10058838
申请日：2002-01-28
CPC分类号： G11C7/1063 , G06F13/1668 , G11C7/1051
摘要： An apparatus and a method to track command signal occurrence for DRAM data transfer have been disclosed. In one embodiment, the apparatus includes an interface to couple to a data bus, the data bus to transfer data between the interface and one or more memory devices, and a logic unit to generate a command occurrence signal to identify when a command signal is issued, wherein a set of data transfer operations on one of the one or more memory devices are completed in response to the command occurrence signal, a transition of a flag signal, and a chip select signal corresponding to the one memory device. Other embodiments have been claimed and described.
摘要翻译： 已经公开了用于跟踪用于DRAM数据传送的命令信号发生的装置和方法。 在一个实施例中，该装置包括耦合到数据总线的接口，该数据总线在接口和一个或多个存储器件之间传送数据，以及一个逻辑单元，以产生命令发生信号，以识别何时发出命令信号 其中响应于所述命令发生信号，标志信号的转换和对应于所述一个存储器件的片选信号而完成所述一个或多个存储器件之一上的一组数据传送操作。 已经要求和描述了其它实施例。
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公开(公告)号：US06928494B1
公开(公告)日：2005-08-09
申请号：US09538386
申请日：2000-03-29
CPC分类号： G11C7/10
摘要： A method and apparatus for communicating commands and/or data between two different time domains. In one embodiment, multiple memory commands are placed into one or more FIFOs in a manner that specifies the delays that must take place between execution of the different commands. Along with the commands, delay information is placed into the FIFOs, specifying the number of clock cycles, or other form of time delay, that must elapse between execution of a command and execution of a subsequent command. This delay information is used to delay the execution of the subsequent command for the specified time period, while minimizing or eliminating any excess delays. Cue information can also be placed into the FIFOs with the commands to specify which commands must wait for other commands before beginning execution. The delay and cue information is determined and created in the time domain that initiates the transfers. The delays and cueing are executed in the other time domain. Although the different commands may be delivered through different FIFOs and can therefore have unpredictable arrival times with respect to each other, the delay and cueing information maintains the proper execution order and timing between the commands. Interactive control logic at the output of each FIFO uses the timing data to maintain execution in the proper order and with the proper inter-command delays.
摘要翻译： 一种用于在两个不同时域之间传送命令和/或数据的方法和装置。 在一个实施例中，多个存储器命令以指定在不同命令的执行之间必须发生的延迟的方式被放置到一个或多个FIFO中。 与命令一起，将延迟信息放入FIFO中，指定执行命令和执行后续命令之间必须经过的时钟周期数量或其他形式的时间延迟。 该延迟信息用于在指定的时间段内延迟后续命令的执行，同时最小化或消除任何多余的延迟。 提示信息也可以放在FIFO中，其命令用于指定哪些命令在开始执行之前必须等待其他命令。 在启动传输的时域中确定和创建延迟和提示信息。 延迟和提示在其他时间域执行。 虽然不同的命令可以通过不同的FIFO传递，并且因此可以相对于彼此具有不可预测的到达时间，但延迟和提示信息保持命令之间的正确的执行顺序和定时。 每个FIFO的输出端的交互控制逻辑使用定时数据来维持正确顺序的执行和适当的指令间延迟。
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公开(公告)号：US06925013B2
公开(公告)日：2005-08-02
申请号：US10786940
申请日：2004-02-24
CPC分类号： G06F13/1626 , G06F12/04
摘要： A data mask map may be programmed into a storage device in various ways. In one embodiment, the data mask is hardwired into a selection device to reorder either the data mask bits or the data chunks. In another embodiment, a data mask map is retrieved from a location in memory. In still another embodiment, the data mask map is determined through an algorithm.
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公开(公告)号：US06829184B2
公开(公告)日：2004-12-07
申请号：US10058567
申请日：2002-01-28
IPC分类号： G11C700
CPC分类号： G11C7/22 , G11C7/1072 , G11C11/4076
摘要： A technique to encode a precharge command on a flag signal used to execute data transfer to and from a DRAM.
摘要翻译： 用于对用于执行到DRAM的数据传送的标志信号对预充电命令进行编码的技术。
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15.发明授权Circuit and method for merging refresh and access operations for a memory device 有权用于合并存储器件的刷新和访问操作的电路和方法公开(公告)号：US06463001B1
公开(公告)日：2002-10-08
申请号：US09663042
申请日：2000-09-15
申请人： Michael W. Williams
发明人： Michael W. Williams
IPC分类号： G11C700
CPC分类号： G11C11/406 , G06F13/1636
摘要： A memory controller to generate refresh requests for by storing the status of memory rows and an arithmetic logic unit to store a second status of all the memory rows of all the memory devices in the system memory configuration. A second logic unit stores the open status of the plurality of memory banks. The third logic generates a refresh request based on the open status and the second status in response to a refresh frequency.
摘要翻译： 存储器控制器，用于通过存储存储器行的状态和算术逻辑单元来产生刷新请求，以将所有存储器件的所有存储器行的第二状态存储在系统存储器配置中。 第二逻辑单元存储多个存储体的打开状态。 第三逻辑基于刷新频率基于打开状态和第二状态产生刷新请求。
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16.发明授权Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices 有权用于支持大量存储器件的存储器子系统中的存储器地址解码的方法和装置公开(公告)号：US06252821B1
公开(公告)日：2001-06-26
申请号：US09474570
申请日：1999-12-29
IPC分类号： G11C800
CPC分类号： G11C8/10
摘要： One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group of memory devices, each of the memory devices in the group having the same configuration. A group number is generated that represents an addressed group that contains an addressed memory device that contains the memory access address. A device number is generated that represents the location of the addressed memory device within the addressed group. A device selection signal is generated responsive to the group number and the device number.
摘要翻译： 本发明的一个实施例是用于对存储器访问地址进行解码的方法。 将存储器访问地址的一部分与多个边界值进行比较，多个边界值中的每一个表示一组存储器设备的最高地址，组中的每个存储器件具有相同的配置。 生成组号，其表示包含存储器访问地址的寻址存储器设备的寻址组。 生成一个设备编号，表示寻址的组中寻址的存储器件的位置。 根据组号和设备编号产生设备选择信号。
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公开(公告)号：US5908982A
公开(公告)日：1999-06-01
申请号：US45963
申请日：1998-03-18
CPC分类号： G01M13/027 , F04B51/00
摘要： A test apparatus for testing the performance of a rotary drive includes a aft which extends along a longitudinal axis, at least one support for supporting the shaft in an elevated position, and a flywheel of predetermined weight rotatably attached to the shaft so that upon rotation of the shaft the flywheel rotates as well. A rotary drive powers the rotation of the shaft and flywheel, the rotary drive having a hydraulic motor which is in fluid communication with a reservoir containing hydraulic fluid by way of a servo valve. A microprocessor controls the rotation of the shaft by the rotary drive. The test apparatus further includes a rotary encoder, a torque sensor, and pressure sensors for monitoring the angular displacement of the system, the torque on the shaft, and various system pressures respectively.
摘要翻译： 用于测试旋转驱动器的性能的测试装置包括沿着纵向轴线延伸的轴，用于将轴支撑在升高位置的至少一个支撑件和可旋转地附接到轴的预定重量的飞轮，使得在旋转 飞轮也转动轴。 旋转驱动器驱动轴和飞轮的旋转，旋转驱动器具有液压马达，其通过伺服阀与包含液压流体的储存器流体连通。 微处理器通过旋转驱动器控制轴的旋转。 测试装置还包括旋转编码器，转矩传感器和用于监测系统的角位移，轴上的转矩和各种系统压力的压力传感器。
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公开(公告)号：US20090249169A1
公开(公告)日：2009-10-01
申请号：US12058076
申请日：2008-03-28
IPC分类号： G11C29/00
CPC分类号： G11C11/406 , G06F11/106 , G11C7/1006 , G11C7/1045 , G11C11/40615 , G11C11/40618 , G11C2029/0411 , G11C2211/4061 , G11C2211/4062
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some embodiments, the refresh frequency of a DRAM is reduced and errors are allowed to occur. In error check mode, the DRAM stores data and corresponding error check bits. The error check bits may be used to scrub the memory and fix the errors.
摘要翻译： 本发明的实施例一般涉及用于保存动态随机存取存储器（DRAM）自刷新功率的系统，方法和装置。 在一些实施例中，DRAM的刷新频率降低并且允许发生错误。 在错误检查模式下，DRAM存储数据和相应的错误校验位。 错误校验位可用于擦除内存并修复错误。
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公开(公告)号：US20080151591A1
公开(公告)日：2008-06-26
申请号：US11644607
申请日：2006-12-21
CPC分类号： G11C5/04
摘要： In some embodiments, a chip includes transmitter circuitry, receiver circuitry, and control circuitry to detect whether a memory module is coupled to the receiver circuitry. The control circuitry selectively provides memory chip configuration signals to the transmitter circuitry to be provided to memory chips to control how many interface lanes in the memory chips are to be used to carry read data in response to a read request and whether some of the interface lanes are used for carrying read data signals or command signals. Other embodiments are described.
摘要翻译： 在一些实施例中，芯片包括发射器电路，接收器电路和控制电路，以检测存储器模块是否耦合到接收器电路。 控制电路选择性地向发射机电路提供存储器芯片配置信号以提供给存储器芯片，以控制存储器芯片中的多少个接口通道将被用于响应于读取请求而携带读取数据，以及一些接口通道 用于承载读数据信号或命令信号。 描述其他实施例。
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20.发明授权公开(公告)号：US07243205B2
公开(公告)日：2007-07-10
申请号：US10713784
申请日：2003-11-13
申请人： Chris B. Freeman , Pete D. Vogt , Kuljit S. Bains , Robert M. Ellis , John B. Halbert , Michael W. Williams
发明人： Chris B. Freeman , Pete D. Vogt , Kuljit S. Bains , Robert M. Ellis , John B. Halbert , Michael W. Williams
IPC分类号： G06F12/00
CPC分类号： G06F13/16
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.
摘要翻译： 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。 缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作 。 例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。 描述和要求保护其他实施例。
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