公开(公告)号：US06466520B1

公开(公告)日：2002-10-15

申请号：US09244753

申请日：1999-02-05

申请人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

发明人： Gil A. Speyer ,  David L. Ferguson ,  Daniel Y. Chung ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

IPC分类号： G04F800

CPC分类号： G01R31/3016 ,  G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/318516

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 相位鉴别器对振荡器的输出进行采样，并累加表示通过测试电路传播的上升或下降信号转换的信号传播延迟的数据。 与测试电路相关的最坏情况延迟可以表示为两者中较长的时间。 了解精确的最坏情况延迟允许IC设计者将保护带最小化，从而保证更高的速度性能。

公开(公告)号：US6069849A

公开(公告)日：2000-05-30

申请号：US115138

申请日：1998-07-14

申请人： Christopher H. Kingsley ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

发明人： Christopher H. Kingsley ,  Robert D. Patrie ,  Robert W. Wells ,  Robert O. Conn

IPC分类号： G01R27/04 ,  G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  G04F8/00 ,  G01R15/12

CPC分类号： G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the average period of the oscillator. Finally, the average period of the oscillator is related to the average signal propagation delay through the test circuit. A phase discriminator samples the output of the oscillator and accumulates data representing the duty cycle of that signal. The duty cycle can then be combined with the average period of the test signal to determine, separately, the delays associated with falling and rising edges propagating through the test circuit.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 这些信号转换在预定的时间周期内进行计数以建立振荡器的平均周期。 最后，振荡器的平均周期与通过测试电路的平均信号传播延迟有关。 相位鉴别器对振荡器的输出采样，并累加表示该信号占空比的数据。 然后可以将占空比与测试信号的平均周期组合，以分别确定与通过测试电路传播的下降沿和上升沿相关联的延迟。

公开(公告)号：US06594797B1

公开(公告)日：2003-07-15

申请号：US09521947

申请日：2000-03-09

申请人： Rick W. Dudley ,  Jae Cho ,  Robert D. Patrie ,  Robert W. Wells

发明人： Rick W. Dudley ,  Jae Cho ,  Robert D. Patrie ,  Robert W. Wells

IPC分类号： G06F1100

CPC分类号： G01R31/31937 ,  G01R31/318516 ,  G01R31/3191

摘要： Described are methods and circuits for accurately placing signal transitions, or “edges,” simultaneously on two or more pins of an integrated circuit (IC). A conventional tester is connected to an integrated circuit, such as a programmable logic device. The integrated circuit is adapted to include a coincidence detector that compares the timing of edges on two input pins of the integrated circuit. The coincidence detector indicates when the two edges are coincident, allowing an operator of the tester to adjust the tester to establish coincidence. The amount of offset necessary to provide coincident edges is stored in a database for later use in deskewing edges used in subsequent tests. The integrated circuit can be a programmable logic device configured to include one or more coincidence detectors with which to place edges relative to one another on different pins.

摘要翻译： 描述了用于在集成电路（IC）的两个或更多个引脚上同时精确地放置信号转换或“边沿”的方法和电路。 常规的测试器连接到诸如可编程逻辑器件的集成电路。 集成电路适于包括比较集成电路的两个输入引脚上的边沿的定时的重合检测器。 重合检测器指示两个边缘何时重合，允许测试仪的操作者调整测试仪以建立巧合。 提供重合边缘所需的偏移量存储在数据库中，以供以后用于后续测试中使用的偏移校正边缘。 集成电路可以是可编程逻辑器件，其被配置为包括一个或多个重合检测器，用于在不同的引脚上相对于彼此放置边缘。

公开(公告)号：US06594610B1

公开(公告)日：2003-07-15

申请号：US09853351

申请日：2001-05-11

申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

IPC分类号： G06F1900

CPC分类号： G01R31/318519 ,  G01R31/318342

摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。

公开(公告)号：US06539508B1

公开(公告)日：2003-03-25

申请号：US09526138

申请日：2000-03-15

申请人： Robert D. Patrie ,  Robert W. Wells

发明人： Robert D. Patrie ,  Robert W. Wells

IPC分类号： H04B1700

CPC分类号： G01R31/318516

摘要： Described is a test circuit that can be instantiated on a programmable logic device to perform at-speed functional tests of programmable resources, including internal memory and routing resources. The resources to be tested are configured to instantiate a counter circuit connected to the address terminals of a linear-feedback shift register (LFSR). LFSRs are cyclic, in the sense that when clocked repeatedly they go through a fixed sequence of states. Consequently, an LFSR that starts with a known set of data has a predictable set of data after a given number of clock periods. The LFSR is preset to a known count and clocked a known number of times. The resulting count is then compared with a reference. If the resulting count matches the reference, then all of the resources used to implement the test circuit, including the memory and routing resources used to implement the LFSR, are deemed fully functional at the selected clock speed. A test circuit employing an LFSR can be duplicated many times on a given device under test to consume (and therefore test) as many resources as possible.

摘要翻译： 描述了可以在可编程逻辑器件上实例化的测试电路，以执行包括内部存储器和路由资源在内的可编程资源的高速功能测试。 要测试的资源被配置为实例化连接到线性反馈移位寄存器（LFSR）的地址端子的计数器电路。 在这种意义上，当重复时钟时，LFSR是循环的，它们经历固定的状态序列。 因此，以已知数据集开始的LFSR在给定数量的时钟周期之后具有可预测的数据集合。 LFSR预设为已知的计数，并且已知次数。 然后将得到的计数与参考值进行比较。 如果结果计数与引用匹配，则用于实现测试电路的所有资源（包括用于实现LFSR的存储器和路由资源）被视为在所选择的时钟速度下完全正常工作。 使用LFSR的测试电路可以在给定的被测设备上重复许多次以消耗尽可能多的资源（并因此测试）。

公开(公告)号：US06356514B1

公开(公告)日：2002-03-12

申请号：US09816712

申请日：2001-03-23

申请人： Robert W. Wells ,  Robert D. Patrie ,  Robert O. Conn

发明人： Robert W. Wells ,  Robert D. Patrie ,  Robert O. Conn

IPC分类号： G04F800

CPC分类号： G01R31/3016 ,  G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/318516 ,  G01R31/31937

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 这些信号转换在预定的时间周期内进行计数，以建立振荡器的周期。 然后振荡器的周期与通过测试电路的平均信号传播延迟相关。 本发明可以应用于通过将异步设置或清除端子连接到输出端子而可能无法振荡的同步部件，使得振荡器以由那些部件的时钟到输出延迟确定的频率振荡。 因此，该配置可以用于表征同步和异步组件，以提供用于预测包括那些或类似组件的电路的定时行为的数据。

公开(公告)号：US06233205B1

公开(公告)日：2001-05-15

申请号：US09115204

申请日：1998-07-14

申请人： Robert W. Wells ,  Robert D. Patrie ,  Robert O. Conn

发明人： Robert W. Wells ,  Robert D. Patrie ,  Robert O. Conn

IPC分类号： G04F800

CPC分类号： G01R31/3016 ,  G01R27/04 ,  G01R31/2853 ,  G01R31/2882 ,  G01R31/31725 ,  G01R31/318516 ,  G01R31/31937

摘要： A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. These signal transitions are counted over a predetermined time period to establish the period of the oscillator. The period of the oscillator is then related to the average signal propagation delay through the test circuit. The invention can be applied to synchronous components that might fail to oscillate by connecting the asynchronous set or clear terminal to the output terminal so that the oscillator oscillates at a frequency determined by the clock-to-out delay of those components. The configuration can thus be used to characterize synchronous and asynchronous components to provide data for predicting the timing behavior of circuits that include those or similar components.

摘要翻译： 电路通过选定的测试电路测量信号传播延迟。 测试电路设置有反馈路径，使得测试电路和反馈路径一起形成自由振荡的振荡器。 然后振荡器自动提供自己的测试信号，包括在测试电路输入节点上交替的上升和下降信号转换。 这些信号转换在预定的时间周期内进行计数，以建立振荡器的周期。 然后振荡器的周期与通过测试电路的平均信号传播延迟相关。 本发明可以应用于通过将异步设置或清除端子连接到输出端子而可能无法振荡的同步部件，使得振荡器以由那些部件的时钟到输出延迟确定的频率振荡。 因此，该配置可以用于表征同步和异步组件，以提供用于预测包括那些或类似组件的电路的定时行为的数据。

公开(公告)号：US6023565A

公开(公告)日：2000-02-08

申请号：US805378

申请日：1997-02-24

申请人： Gary R. Lawman ,  Joseph D. Linoff ,  Robert W. Wells

发明人： Gary R. Lawman ,  Joseph D. Linoff ,  Robert W. Wells

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of specifying design parameters is provided for configuring circuits for programmable ICs. A design database describing a circuit is displayed in table-based format on a computer screen display. The design database may include a memory map including data to be placed in bit-storage space in the target programmable IC. This design database requires no schematics or HDL description of the circuit, even for complicated application-specific circuits. The desired parameters are entered by the user, typically using toggle buttons, pull-down menus, or keyboard entry. The selected parameters are then entered into the design database, thereby configuring the design database in accordance with the selected parameters. Next, the design database is transmitted over a data communications link such as the internet to a second computer, on which the compilation software resides. The design is then compiled and the resulting netlist is transmitted back to the originating computer. In one embodiment, a schematic symbol or HDL instantiation is also generated by the second computer, and transmitted back to the originating computer.

摘要翻译： 提供了一种指定设计参数的方法，用于配置可编程IC的电路。 描述电路的设计数据库在计算机屏幕显示器上以基于表格的格式显示。 设计数据库可以包括存储图，包括要放置在目标可编程IC中的位存储空间中的数据。 该设计数据库不需要电路的原理图或HDL描述，即使对于复杂的应用特定电路也是如此。 所需的参数由用户输入，通常使用切换按钮，下拉菜单或键盘输入。 然后将选定的参数输入设计数据库，从而根据所选参数配置设计数据库。 接下来，将设计数据库通过诸如因特网的数据通信链路传送到编译软件所在的第二计算机。 然后编译设计，并将所得到的网表传回原始计算机。 在一个实施例中，示意符号或HDL实例化也由第二计算机产生，并被发送回始发计算机。

公开(公告)号：US07725787B1

公开(公告)日：2010-05-25

申请号：US12235489

申请日：2008-09-22

申请人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Shekhar Bapat ,  Tassanee Payakapan ,  Shahin Toutounchi

IPC分类号： G01R31/28

CPC分类号： G01R31/318519 ,  G01R31/31707

摘要： A method of testing a programmable device begins by programming at least a portion of the programmable device in accordance with at least a portion of an application to produce a programmed circuit, wherein the programmed circuit includes an input sequential element and an output sequential element. The method continues by providing a test input to the programmed circuit. The method continues by triggering the input sequential element to temporarily store the test input based on a first edge of the test clock. The method continues by triggering the output sequential element to temporarily store a test output of the programmed circuit based on a second edge of the test clock. The method continues by capturing the test output of the programmed circuit in accordance with the second edge of the test clock.

摘要翻译： 测试可编程设备的方法开始于根据应用的至少一部分编程可编程设备的至少一部分以产生编程电路，其中编程电路包括输入顺序元件和输出顺序元件。 该方法通过向编程的电路提供测试输入来继续。 该方法通过触发输入顺序元件来基于测试时钟的第一边临时存储测试输入来继续。 该方法继续通过触发输出顺序元件来临时存储基于测试时钟的第二边缘的编程电路的测试输出。 该方法通过根据测试时钟的第二个边沿捕获编程电路的测试输出来继续。

公开(公告)号：US06664808B2

公开(公告)日：2003-12-16

申请号：US09924365

申请日：2001-08-07

申请人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

发明人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

IPC分类号： H03K19177

CPC分类号： G01R31/318519

摘要： FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.