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公开(公告)号：US11870615B2
公开(公告)日：2024-01-09
申请号：US17835373
申请日：2022-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyeongjoon Ko , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H04L25/03057 , H03K3/037 , H03K19/20
Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.
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公开(公告)号：US11632604B2
公开(公告)日：2023-04-18
申请号：US16876376
申请日：2020-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungbum Park , Kyungwoo Lee , Jaehyun Park , Sungku Yeo , Jeongman Lee
IPC: H04Q9/00 , G01R21/133 , H02J50/10 , H02J50/00
Abstract: A sensor device is provided. The sensor device includes an energy harvester configured to generate electric energy, a monitoring circuit, a sensor, a communication circuit, and at least one processor configured to obtain information indicating a magnitude of the generated electric energy via the monitoring circuit, obtain a sensing value via the sensor, and transmit the sensing value and the information indicating the magnitude of the generated electric energy via the communication circuit to the other electronic device.
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公开(公告)号：US10966106B2
公开(公告)日：2021-03-30
申请号：US16146626
申请日：2018-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bokkeun Kim , Jaehyun Park , Weyoung Yoon , Sujeong Lee , Sungmo Jung , Hangsuk Huh , Kyupyo Hong
Abstract: The present disclosure relates to a method and an apparatus for managing a PDN connection by inducing, by a node, a terminal to autonomously recover a failure situation or detecting the corresponding terminal when the terminal is not capable of generating or maintaining the PDN connection in a wireless communication system and the method of the present disclosure includes: detecting, by a node, a terminal in which a failure occurs in a PDN connection; and transmitting a detach request message to the terminal in which the failure occurs.
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公开(公告)号：US10070317B2
公开(公告)日：2018-09-04
申请号：US14738237
申请日：2015-06-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Heyyoung Park , Jaehyun Park , Jaeyoung Shin
Abstract: A method and apparatus of notifying of SMiShing-related information is provided. The method of notifying of SMiShing by an electronic device includes: transmitting at least one item of message-related information about a received message to a SMiShing detection server; receiving SMiShing-related information about the message from the SMiShing detection server; and displaying content of the message and the received SMiShing-related information when a request is made to display the message.
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15.发明公开公开(公告)号：US20240302432A1
公开(公告)日：2024-09-12
申请号：US18597499
申请日：2024-03-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hobin SONG , Juyun Lee , Jiyoung Kim , Jaehyun Park , Sooeun Lee , Insik Hwang
IPC: G01R31/3183 , G01R31/317 , G01R31/3187 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081
CPC classification number: G01R31/318328 , G01R31/31724 , G01R31/3187 , H03K5/13 , H03L7/0807 , H03K2005/00052 , H03L7/0812
Abstract: A system-on-chip includes a clock generation circuit configured to generate a reference clock of a first phase; a transmission circuit comprising a serializer configured to serialize data according to the reference clock of the first phase; a reception circuit comprising a clock data recovery (CDR) circuit configured to receive the serialized data and generate a first recovery clock and recovery data; and a Built In Self Test (BIST) circuit including a CDR performance monitoring circuit configured to generate a control signal provided to a delay controller configured to delay a clock signal by a preset phase difference, and the delay controller configured to delay the clock signal in response to the control signal by the preset phase difference and provide the delayed clock signal to the transmission circuit.
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Patent Agency Ranking
公开(公告)号：US12074449B2
公开(公告)日：2024-08-27
申请号：US17956443
申请日：2022-09-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Beomwoo Gu , Jaeseok Park , Jaehyun Park , Youngho Ryu , Jungkyu Han
CPC classification number: H02J50/12 , H03H1/00 , H03H2001/0035
Abstract: An example wireless power transmitter may include a transistor configured to output an amplified signal, a first capacitor coupled to the transistor in parallel, a first LC resonant circuit coupled to the transistor in parallel, a third capacitor having a first end coupled to an output terminal of the transistor and the first LC resonant circuit, a feeding coil coupled to a second end of the third capacitor in series, and having at least a part configured to form a second LC resonant circuit with the third capacitor, and a transmission resonator including a transmission coil and a fourth capacitor coupled to the transmission coil in series. At least a part of the transmission coil may be magnetically coupled with the feeding coil, and at least a part of power received from the feeding coil may be output to an outside through the transmission resonator.
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公开(公告)号：US12003250B2
公开(公告)日：2024-06-04
申请号：US17837752
申请日：2022-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H03M1/682 , H03M1/687 , H03M1/747 , H03M1/0617 , H03M1/66
Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.
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公开(公告)号：US11973623B2
公开(公告)日：2024-04-30
申请号：US17834563
申请日：2022-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Hanseok Kim , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H04L25/03057 , H04B1/16 , H04L25/03878 , H04L2025/03445
Abstract: A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.
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公开(公告)号：US11600340B2
公开(公告)日：2023-03-07
申请号：US17462298
申请日：2021-08-31
Inventor： Seungwoo Seo , Byeongho Kim , Jaehyun Park , Jungho Ahn , Minbok Wi , Sunjung Lee , Eojin Lee , Wonkyung Jung , Jongwook Chung , Jaewan Choi
Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
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20.发明授权公开(公告)号：US11456851B2
公开(公告)日：2022-09-27
申请号：US17469062
申请日：2021-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hanseok Kim , Hobin Song , Jaehyun Park
Abstract: A clock data recovery circuit includes a phase locked loop (PLL), a code signal generator, and a clock and data generator. The PLL generates a plurality of reference clock signals of which frequencies are modulated. Each of the plurality of reference clock signals has a first profile that is periodically fluctuated. The code signal generator generates a first compensation code signal. The first compensation code signal has a second profile that is periodically fluctuated and is different from the first profile. The clock and data generator generates a recovered data signal by sampling an input data signal based on a clock signal, compensates a frequency modulation on the plurality of reference clock signals based on the first compensation code signal, and includes a phase interpolator that generates the clock signal based on the plurality of reference clock signals and the first compensation code signal.
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