公开(公告)号：US20230217661A1

公开(公告)日：2023-07-06

申请号：US17961070

申请日：2022-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbum WOO ,  Joonsung LIM ,  Junhyoung KIM ,  Seungmin LEE

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11573 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.

公开(公告)号：US20220399360A1

公开(公告)日：2022-12-15

申请号：US17721533

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoon SON ,  Junhyoung KIM

IPC: H01L27/11573 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

Abstract: A semiconductor device and a data storage system including the same are provided. The semiconductor device including a plate layer, a pattern structure on the plate layer, an upper pattern layer on the pattern structure, an upper structure including a stack structure and a capping insulating structure covering at least a portion of the stack structure, the stack structure including interlayer insulating layers and gate layers alternately stacked on each other, and separation structures and vertical memory structures penetrating through the upper structure, the upper pattern layer, and the pattern structure, and extending into the plate layer may be provided.

公开(公告)号：US20210399010A1

公开(公告)日：2021-12-23

申请号：US17204010

申请日：2021-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Youngjin KWON ,  Jeongeun KIM ,  Byunggon PARK ,  Sungwon CHO

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11595 ,  H01L23/528

Abstract: A memory device includes a lower structure, a stacked structure on the lower structure, the stacked structure including horizontal layers and interlayer insulating layers alternately stacked in a vertical direction, and each of the horizontal layers including a gate electrode, a vertical structure penetrating through the stacked structure in the vertical direction, the vertical structure having a core region, a pad pattern with a pad metal pattern on the core region, a dielectric structure including a first portion facing a side surface of the core region, a second portion facing at least a portion of a side surface of the pad metal pattern, and a data storage layer, and a channel layer between the dielectric structure and the core region, a contact structure on the vertical structure, and a conductive line on the contact structure.

公开(公告)号：US20250167115A1

公开(公告)日：2025-05-22

申请号：US18925771

申请日：2024-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jimo GU ,  Bumkyu KANG ,  Ahreum LEE ,  Junhyoung KIM ,  Jiwon KIM ,  Sukkang SUNG

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B12/00 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

Abstract: A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.

公开(公告)号：US20250070029A1

公开(公告)日：2025-02-27

申请号：US18943201

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Joongshik SHIN ,  Kwangsoo KIM

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A three-dimensional semiconductor device may include a substrate having a cell area and an extension area, a word line stack disposed above the substrate, the word line stack including mold layers and word lines alternately stacked, vertical channel structures vertically penetrating the word line stack in the cell area, and a first extension through-via structure vertically penetrating the word line stack in the extension area. The first extension through-via structure may include a first via plug and a first via liner layer surrounding sidewalls of the first via plug. The first via liner layer may include first dents respectively disposed at the same levels horizontally as the word lines of the word line stack.

公开(公告)号：US20220216226A1

公开(公告)日：2022-07-07

申请号：US17497200

申请日：2021-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moorym CHOI ,  Taemok GWON ,  Junhyoung KIM ,  Hyunjae KIM ,  Youngbum WOO ,  Jongin YUN

IPC: H01L27/11556 ,  H01L23/538 ,  H01L27/11582 ,  G11C5/06 ,  H01L29/06

Abstract: A semiconductor device includes a first substrate including an impurity region including impurities of a first conductivity type, circuit devices on the first substrate, a lower interconnection structure electrically connected to the circuit devices, a second substrate on the lower interconnection structure and including semiconductor of the first conductivity type, gate electrodes on the second substrate and stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, channel structures penetrating the gate electrodes, and a connection structure. The channel structures may extend perpendicular to the second substrate. The channel structures may include a channel layer. The connection structure may connect the impurity region of the first substrate to the second substrate, and the connection structure may include a via including a semiconductor of a second conductivity type.

公开(公告)号：US20220093629A1

公开(公告)日：2022-03-24

申请号：US17242696

申请日：2021-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Chanho KIM ,  Kyunghwa YUN ,  Dongseong KIM

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11526 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device and an electronic system, the semiconductor device including a semiconductor substrate; a peripheral circuit structure including peripheral circuits integrated on the semiconductor substrate, and a landing pad connected to the peripheral circuits; a semiconductor layer on the peripheral circuit structure; a metal structure in contact with a portion of the semiconductor layer, the metal structure including first portions extending in a first direction, second portions connected to the first portions and extending in a second direction crossing the first direction, and a via portion vertically extending from at least one of the first and second portions and being connected to the landing pad; and a stack including insulating layers and electrodes vertically and alternately stacked on the metal structure.

公开(公告)号：US20210043648A1

公开(公告)日：2021-02-11

申请号：US16850097

申请日：2020-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Seonho YOON ,  Bonghyun CHOI

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a substrate with a cell region, a through via region on opposite sides of the cell region, and a mold region surrounding the cell and through via regions, gate electrodes spaced apart from each other along a first direction vertical to an upper surface of the substrate, and extending in a second direction parallel to the upper surface of the substrate, a channel extending in the first direction on the cell region, and extending through at least a portion of the stacked gate electrodes, and a first mold including first and second layers alternately and repeatedly stacked along the first direction on the mold region, the first and second layers including different insulation materials from each other, and each of the second layers of the first mold being at the same height as and contact a corresponding one of the gate electrodes.

公开(公告)号：US20210005620A1

公开(公告)日：2021-01-07

申请号：US16835559

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyoung KIM ,  Jisung CHEON

IPC: H01L27/11524 ,  H01L27/11582 ,  H01L27/11548

Abstract: A semiconductor device including vertical structures on a substrate; and interlayer insulating layers and gate layers on the substrate, wherein the gate layers are sequentially stacked in a memory cell array area and extend into an extension area, the gate layers have pad regions having a staircase structure in the extension area, the first vertical structure has a surface facing the gate layers, the second vertical structure has a surface facing at least one of the gate layers, the first vertical structure includes a first core pattern, a first semiconductor layer, and a pad pattern, the second vertical structure includes a second core pattern and a second semiconductor layer, each of the core patterns includes an insulating material, and an upper surface of the second semiconductor layer and an upper surface of the second core pattern are farther from the substrate than the upper surface of the first core pattern.

公开(公告)号：US20250056806A1

公开(公告)日：2025-02-13

申请号：US18610514

申请日：2024-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung KIM ,  Bumkyu KANG ,  Junyong PARK ,  Sukkang SUNG

IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device and a data storage system are provided. The semiconductor device includes a peripheral circuit structure; a stack structure vertically overlapping the peripheral circuit structure; and a separation structure penetrating through the stack structure. The stack structure includes a plurality of blocks spaced apart from each other by a first portion of the separation structure, each of the plurality of blocks includes insulating layers and conductive layers alternately stacked in a vertical direction, and the plurality of blocks include first blocks and a plurality of capacitor blocks disposed between first blocks adjacent to each other among the first blocks.