中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

26 records (took 0.021 seconds)

    Non-volatile memory device for detecting defects of bit lines and word lines
    11.
    发明授权
    Non-volatile memory device for detecting defects of bit lines and word lines 有权

    公开(公告)号：US12131798B2

    公开(公告)日：2024-10-29

    申请号：US17972300

    申请日：2022-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

    IPC: G11C7/10 ,  G06F11/10

    CPC classification number: G11C7/1057 ,  G06F11/1076

    Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

    Semiconductor devices
    13.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11373942B2

    公开(公告)日：2022-06-28

    申请号：US16826995

    申请日：2020-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung Ko ,  Senyun Kim ,  Younghoon Ro

    IPC: H01L23/498 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

    VOLATILE MEMORY DEVICES AND METHODS OF OPERATING SAME TO IMPROVE RELIABILITY
    14.
    发明公开
    VOLATILE MEMORY DEVICES AND METHODS OF OPERATING SAME TO IMPROVE RELIABILITY 审中-公开

    公开(公告)号：US20240212775A1

    公开(公告)日：2024-06-27

    申请号：US18347631

    申请日：2023-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

    IPC: G11C29/12

    CPC classification number: G11C29/12005

    Abstract: A volatile memory device includes an array of memory cells electrically coupled to a plurality of word lines and a plurality of bitlines, and a bitline sense amplifier electrically coupled to the plurality of bitlines. Control logic is provided, which is configured to control: (i) consecutive self-refresh operations within the array of memory cells that are spaced apart from each other by a first period, (ii) storage of dummy data within the array of memory cells during operations to predict life expectancy of memory cells therein, (iii) consecutive test refresh operations within the array of memory cells that are spaced apart from each other by a second period greater than the first period, and (iv) performance of a test sensing operation on selected memory cells within the array using the bitline sense amplifier. A deterioration detection circuit is provided, which is configured to receive sensing results associated with the selected memory cells from the bitline sense amplifier, and to output multi-bit-count current having a magnitude proportional to a number of deteriorated memory cells among the selected memory cells, based on the sensing results.

    CXL DEVICES AND OPERATION METHODS OF CXL DEVICES
    15.
    发明公开
    CXL DEVICES AND OPERATION METHODS OF CXL DEVICES 审中-公开

    公开(公告)号：US20240168848A1

    公开(公告)日：2024-05-23

    申请号：US18330631

    申请日：2023-06-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Changhwi Park ,  Junyoung Ko ,  Jungmin Bak

    IPC: G06F11/10 ,  G06F11/00 ,  G06F11/30

    CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/3072

    Abstract: Embodiments of the present invention provide a CXL device including a plurality of memories; a memory management unit configured to: configure at least one tier group in which the plurality of memories are classified and included; determine, based on metadata of a first memory of the plurality of memories, a grade of the first memory; and determine a tier group, to which the first memory belongs, of the at least one tier group according to the grade; and a memory processing unit configured to store data in at least one of the plurality of memories included in the at least one tier group, based on tiering information of the data.

    MEMORY DEVICE INCLUDED IN MEMORY SYSTEM AND METHOD FOR DETECTING FAIL MEMORY CELL THEREOF
    16.
    发明公开
    MEMORY DEVICE INCLUDED IN MEMORY SYSTEM AND METHOD FOR DETECTING FAIL MEMORY CELL THEREOF 审中-公开

    公开(公告)号：US20240079074A1

    公开(公告)日：2024-03-07

    申请号：US18332948

    申请日：2023-06-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin Bak ,  Junyoung Ko ,  Changhwi Park

    IPC: G11C29/02 ,  G11C7/10 ,  G11C29/52

    CPC classification number: G11C29/022 ,  G11C7/1096 ,  G11C29/52

    Abstract: A memory device includes a memory cell array including a plurality of memory cells, a word line defect detection circuit electrically connected to the memory cell array through a plurality of word lines, and control logic configured to control an input/output operation of the memory cell array. When a memory defect detection command is received from a memory controller, the word line defect detection circuit is configured to provide an input voltage to a selected word line among the plurality of word lines, and to generate a fail flag based on a difference between a voltage of the selected word line and a reference voltage. When a mode register read command is received from the memory controller, the control logic is configured to transmit the fail flag and a fail row address corresponding to the fail flag to the memory controller.

    MEMORY CONTROL DEVICE AND REFRESH CONTROL METHOD THEREOF
    17.
    发明公开
    MEMORY CONTROL DEVICE AND REFRESH CONTROL METHOD THEREOF 审中-公开

    公开(公告)号：US20240069757A1

    公开(公告)日：2024-02-29

    申请号：US18312779

    申请日：2023-05-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung Ko ,  Jungmin Bak ,  Changhwi Park

    IPC: G06F3/06

    CPC classification number: G06F3/0623 ,  G06F3/0653 ,  G06F3/0673

    Abstract: A memory control device includes a threshold generating circuit, which is configured to set a first threshold for a first memory module electrically coupled to the memory control device. This first threshold is based on information associated with the first memory module. An attack defense circuit is also provided, which is configured to count an input row address, and decide a row address whose count value exceeds the first threshold among row addresses of the first memory module as an aggressor row address.

    NON-VOLATILE MEMORY DEVICE FOR DETECTING DEFECTS OF BIT LINES AND WORD LINES
    19.
    发明公开
    NON-VOLATILE MEMORY DEVICE FOR DETECTING DEFECTS OF BIT LINES AND WORD LINES 审中-公开

    公开(公告)号：US20230144141A1

    公开(公告)日：2023-05-11

    申请号：US17972300

    申请日：2022-10-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung Ko ,  Sangwan Nam ,  Youse Kim ,  Heewon Kim

    IPC: G11C7/10 ,  G06F11/10

    CPC classification number: G11C7/1057 ,  G06F11/1076

    Abstract: Provided is a non-volatile memory device. The non-volatile memory device includes: a memory cell array including cell strings, each including memory cells respectively connected to word lines; a page buffer circuit including page buffers respectively connected to the memory cells through bit lines, wherein a first page buffer is connected to a first cell string through a first bit line; a control logic circuit configured to control a pre-sensing operation to disconnect the first bit line and the first cell string from each other during a pre-sensing period for detecting a defect of the first bit line and control a post-sensing operation to connect the first bit line and the first cell string to each other in a post-sensing period for detecting defects of the word lines and the first bit line; and a defect detection circuit configured to detect defects of the word lines based the sensing operations.

Patent Agency Ranking