公开(公告)号：US12087650B2

公开(公告)日：2024-09-10

申请号：US18315558

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Hyunggil Baek ,  Seunghwan Kim ,  Jungjoo Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L25/0657

Abstract: A semiconductor package is provided. The semiconductor package includes: a first package substrate; a first semiconductor chip on the first package substrate; an interposer substrate including a lower surface facing the first package substrate, an upper surface opposite to the lower surface, and an upper conductive pad in the upper surface of the interposer substrate; a first dam structure on the upper surface of the interposer substrate and extending along an edge of the upper conductive pad; a first molding layer in contact with the lower and upper surfaces of the interposer substrate and with an outer wall of the first dam structure; and a conductive connector in contact with an inner wall of the at least one first dam structure and with the upper conductive pad.

公开(公告)号：US11742294B2

公开(公告)日：2023-08-29

申请号：US17306290

申请日：2021-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongho Park ,  Seunghwan Kim ,  Junyoung Oh ,  Yonghyun Kim ,  Yongkwan Lee ,  Junga Lee

IPC: H01L23/13 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/5385 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes a first package substrate; a first semiconductor chip on the first package substrate; a first conductive connector on the first package substrate; and an interposer including a central portion on the first semiconductor chip and an outer portion having the first conductive connector attached thereto. The central portion of the interposer includes a bottom surface defining a recess from a bottom surface of the outer portion of the interposer in a vertical direction that is perpendicular to a top surface of the first package substrate. A thickness in the vertical direction of the outer portion of the interposer is greater than a thickness in the vertical direction of the central portion of the interposer.

公开(公告)号：US11508713B2

公开(公告)日：2022-11-22

申请号：US17168706

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung Oh ,  Kyonghwan Koh ,  Sangsoo Kim ,  Seunghwan Kim ,  Jongho Park ,  Yongkwan Lee

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/78 ,  H01L25/065

Abstract: A method of manufacturing a semiconductor package includes forming a laser reactive polymer layer on a substrate; mounting a semiconductor device on the substrate; irradiating at least a portion of the laser reactive polymer layer below the semiconductor device with a laser having a wavelength capable of penetrating through the semiconductor device on the substrate to modify the laser reactive polymer layer to have a hydrophilic functional group; and forming a first encapsulation material layer between the semiconductor device and the substrate.

公开(公告)号：US20200350288A1

公开(公告)日：2020-11-05

申请号：US16680657

申请日：2019-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Kyungsuk Oh ,  Hyunki Kim ,  Yongkwan Lee ,  Sangsoo Kim ,  Seungkon Mok ,  Junyoung Oh ,  Changyoung Yoo

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16

Abstract: A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.