公开(公告)号：US12112783B2

公开(公告)日：2024-10-08

申请号：US17537937

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Pil Ko ,  Yongjae Kim ,  Geonhee Bae ,  Gawon Lee ,  Kilho Lee

IPC: G11C11/16 ,  H01L23/528 ,  H10B61/00 ,  H10N50/10 ,  H10N50/20 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H01L23/528 ,  H10B61/00 ,  H10N50/10 ,  H10N50/20 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.

公开(公告)号：US11665910B2

公开(公告)日：2023-05-30

申请号：US17546107

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H10B61/00 ,  H01L23/522 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/00 ,  H01L23/5226 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US20220102426A1

公开(公告)日：2022-03-31

申请号：US17546107

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/10 ,  H01L43/02

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US11211425B2

公开(公告)日：2021-12-28

申请号：US16895602

申请日：2020-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/10 ,  H01L43/02

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US20240431119A1

公开(公告)日：2024-12-26

申请号：US18405141

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Yongjae Kim ,  Junho Park

IPC: H10B61/00

Abstract: A semiconductor device may include a lower dielectric layer on a substrate, data storage patterns on the lower dielectric layer and spaced apart from each other in first and second directions, a cell dielectric layer on the lower dielectric layer and on the data storage patterns, voids in the cell dielectric layer and between ones of the data storage patterns, upper conductive contacts respectively on the data storage patterns and spaced apart from each other in the first and second directions, and upper conductive lines on the upper conductive contacts and spaced apart from each other in the second direction and extending in the first direction. Each of the upper conductive lines may be electrically connected to respective ones of the upper conductive contacts. The respective ones of the upper conductive contacts may be spaced apart from each other in the first direction.

公开(公告)号：US20210351233A1

公开(公告)日：2021-11-11

申请号：US17381768

申请日：2021-07-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  G11C11/02 ,  G11C11/56

Abstract: A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

公开(公告)号：US20210082998A1

公开(公告)日：2021-03-18

申请号：US16895602

申请日：2020-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L23/522

Abstract: A magnetic memory device includes a magnetic tunnel junction pattern on a substrate, a first conductive pattern between the substrate and the magnetic tunnel junction pattern, lower contact plugs between the first conductive pattern and the substrate and disposed at respective sides of the magnetic tunnel junction pattern, and second conductive patterns on the lower contact plugs, respectively. The second conductive patterns connect the lower contact plugs to the first conductive pattern. The second conductive patterns include a ferromagnetic material.

公开(公告)号：US10861902B2

公开(公告)日：2020-12-08

申请号：US16010447

申请日：2018-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Ilmok Park ,  Junhee Lim

IPC: H01L27/24 ,  H01L27/1157 ,  G11C11/16 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/11575 ,  G11C14/00 ,  G11C5/02 ,  G11C16/04

Abstract: A semiconductor device includes first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

公开(公告)号：US10438998B2

公开(公告)日：2019-10-08

申请号：US15828937

申请日：2017-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Hongsoo Kim ,  Junhee Lim ,  Chang-Hoon Jeon

IPC: G11C5/02 ,  H01L27/24 ,  G11C11/00 ,  H01L45/00 ,  H01L27/11573 ,  G11C13/00 ,  H01L27/22 ,  G11C11/16 ,  H01L43/08 ,  H01L49/02 ,  H01L27/11582

Abstract: Integrated circuit devices may include a substrate including a flash memory region and a variable resistance memory region, a flash memory cell transistor including a cell gate electrode that overlaps the flash memory region of the substrate, a variable resistance element that overlaps the variable resistance memory region of the substrate, and a select transistor including a select source/drain region that is disposed in the variable resistance memory region of the substrate. The select source/drain region may be electrically connected to the variable resistance element. The substrate may include an upper surface facing the cell gate electrode and the variable resistance element, and the upper surface of the substrate may continuously extend from the flash memory region to the variable resistance memory region.

公开(公告)号：US10373653B2

公开(公告)日：2019-08-06

申请号：US15854551

申请日：2017-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kilho Lee ,  Gwanhyeob Koh ,  Junhee Lim ,  Hongsoo Kim ,  Chang-hoon Jeon

IPC: G11C5/06 ,  G11C16/04 ,  G11C11/16 ,  H01L25/18 ,  H01L27/22 ,  H01L27/11573 ,  H01L43/10 ,  H01L27/1157 ,  H01L27/11582

Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.