公开(公告)号：US11688778B2

公开(公告)日：2023-06-27

申请号：US17141513

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20230141852A1

公开(公告)日：2023-05-11

申请号：US17866966

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggil Lee ,  Jungtaek Kim ,  Dohyun Go ,  Pankwi Park ,  Dongsuk Shin ,  Namkyu Cho ,  Ryong Ha ,  Yang Xu

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L21/823814 ,  H01L27/0922

Abstract: A semiconductor device includes a semiconductor active region having a vertical stack of multiple spaced-apart semiconductor channel regions thereon. A gate electrode extends on the active region and between the spaced-apart channel regions. A source/drain region contacts the spaced-apart channel regions. The source/drain region includes a stack of at least first, second and third epitaxial layers having different electrical characteristics. The first epitaxial layer contacts the active region and each of the spaced-apart channel regions. The second epitaxial layer contacts a first portion of an upper surface of the first epitaxial layer. The third epitaxial layer contacts a second portion of the upper surface of the first epitaxial layer. Each of the first, second and third epitaxial layers includes silicon germanium (SiGe) with unequal levels of germanium (Ge) therein. A level of germanium in the third epitaxial layer exceeds a level of germanium in the second epitaxial layer, which exceeds a level of germanium in the first epitaxial layer.

公开(公告)号：US09812557B2

公开(公告)日：2017-11-07

申请号：US15138234

申请日：2016-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Dong-Suk Shin ,  Woon-Ki Shin ,  Cheol-Woo Park ,  Ryong Ha ,  Han-Jin Lim

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02068 ,  H01L21/32134 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method of manufacturing a semiconductor device includes forming an active fin extending longitudinally in a first direction along a surface of a substrate, forming a field insulating layer on the substrate, the field insulating layer covering a part of the active fin, forming a dummy gate electrode on the field insulating layer and the active fin, the dummy gate electrode extending in a second direction different from the first direction, forming a spacer on the sides of the dummy gate electrode, and removing the dummy gate electrode by a wet etching process that includes rinsing the dummy gate electrode intermittently during an etching away of the dummy gate electrode.

公开(公告)号：US12142690B2

公开(公告)日：2024-11-12

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US12027596B2

公开(公告)日：2024-07-02

申请号：US18201308

申请日：2023-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ryong Ha ,  Dongwoo Kim ,  Gyeom Kim ,  Yong Seung Kim ,  Pankwi Park ,  Seung Hun Lee

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/41758 ,  H01L29/1033 ,  H01L29/42356

Abstract: A semiconductor device including an active pattern extending in a first direction; a channel pattern on the active pattern and including vertically stacked semiconductor patterns; a source/drain pattern in a recess in the active pattern; a gate electrode on the active pattern and extending in a second direction crossing the first direction, the gate electrode surrounding a top surface, at least one side surface, and a bottom surface of each of the semiconductor patterns; and a gate spacer covering a side surface of the gate electrode and having an opening to the semiconductor patterns, wherein the source/drain pattern includes a buffer layer covering inner sides of the recess, the buffer layer includes an outer side surface and an inner side surface, which are opposite to each other, and each of the outer and inner side surfaces is a curved surface that is convexly curved toward a closest gate electrode.

公开(公告)号：US20240194789A1

公开(公告)日：2024-06-13

申请号：US18588163

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Taek Kim ,  Seok Hoon Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong ,  Min-Hee Choi ,  Ryong Ha

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: A semiconductor device includes a multi-channel active pattern, a plurality of gate structures on the multi-channel active pattern and spaced apart from each other in a first direction, the plurality of gate structures including a gate electrode that extends in a second direction different from the first direction, a source/drain recess between the adjacent gate structures, and a source/drain pattern on the multi-channel active pattern in the source/drain recess, wherein the source/drain pattern includes: a semiconductor liner layer including silicon-germanium and extending along the source/drain recess, a semiconductor filling layer including silicon-germanium on the semiconductor liner layer, and at least one or more semiconductor insertion layers between the semiconductor liner layer and the semiconductor filling layer, and wherein the at least one or more semiconductor insertion layers have a saddle structure.

公开(公告)号：US11990552B2

公开(公告)日：2024-05-21

申请号：US17533719

申请日：2021-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryong Ha ,  Seok Hoon Kim ,  Jung Taek Kim ,  Pan Kwi Park ,  Moon Seung Yang ,  Seo Jin Jeong

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/78618 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/42392

Abstract: A semiconductor device includes an active pattern which includes a lower pattern, and a sheet pattern that is spaced apart from the lower pattern in a first direction, a gate structure on the lower pattern that includes a gate electrode that surrounds the sheet pattern, the gate electrode extending in a second direction that is perpendicular to the first direction, and a source/drain pattern on the lower pattern and in contact with the sheet pattern. A contact surface between the sheet pattern and the source/drain pattern has a first width in the second direction, and the sheet pattern has a second width in the second direction that is greater than the first width.

公开(公告)号：US20240096945A1

公开(公告)日：2024-03-21

申请号：US18527453

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Choi ,  Seojin Jeong ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Ryong Ha

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/6656 ,  H01L29/78618

Abstract: An integrated circuit device includes a fin-type active region on a substrate; at least one nanosheet having a bottom surface facing the fin top; a gate line on the fin-type active region; and a source/drain region on the fin-type active region, adjacent to the gate line, and in contact with the at least one nanosheet, wherein the source/drain region includes a lower main body layer and an upper main body layer, a top surface of the lower main body layer includes a lower facet declining toward the substrate as it extends in a direction from the at least one nanosheet to a center of the source/drain region, and the upper main body layer includes a bottom surface contacting the lower facet and a top surface having an upper facet. With respect to a vertical cross section, the lower facet extends along a corresponding first line and the upper facet extends along a second line that intersects the first line.

公开(公告)号：US20240030286A1

公开(公告)日：2024-01-25

申请号：US18140905

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Heo ,  Seokhoon Kim ,  Jungtaek Kim ,  Pankwi Park ,  Moonseung Yang ,  Sumin Yu ,  Seojin Jeong ,  Edward Namkyu Cho ,  Ryong Ha

IPC: H01L29/08 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: An integrated circuit device includes a plurality of fin-type active areas extending in a first horizontal direction on a substrate, a plurality of channel regions respectively on the plurality of fin-type active areas, a plurality of gate lines surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction that crosses the first horizontal direction, and a plurality of source/drain regions respectively at positions adjacent to the plurality of gate lines on the plurality of fin-type active areas and respectively in contact with the plurality of channel regions, and the plurality of source/drain regions respectively include a plurality of semiconductor layers and at least one air gap located therein.

公开(公告)号：US11676963B2

公开(公告)日：2023-06-13

申请号：US17584877

申请日：2022-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungryul Lee ,  Yongseung Kim ,  Jungtaek Kim ,  Pankwi Park ,  Dongchan Suh ,  Moonseung Yang ,  Seojin Jeong ,  Minhee Choi ,  Ryong Ha

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/4238 ,  H01L29/785

Abstract: An integrated circuit device includes a fin-type active region protruding from a substrate and extending in a first direction, a plurality of semiconductor patterns disposed apart from an upper surface of the fin-type active region, the plurality of semiconductor patterns each including a channel region; a gate electrode surrounding the plurality of semiconductor patterns, extending in a second direction perpendicular to the first direction, and including a main gate electrode, which is disposed on an uppermost semiconductor pattern of the plurality of semiconductor patterns and extends in the second direction, and a sub-gate electrode disposed between the plurality of semiconductor patterns; a spacer structure disposed on both sidewalls of the main gate electrode; and a source/drain region connected to the plurality of semiconductor patterns, disposed at both sides of the gate electrode, and contacting a bottom surface of the spacer structure.