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    FILM PACKAGE AND DISPLAY MODULE INCLUDING SAME
    11.
    发明公开
    FILM PACKAGE AND DISPLAY MODULE INCLUDING SAME 审中-公开

    公开(公告)号：US20240204009A1

    公开(公告)日：2024-06-20

    申请号：US18237013

    申请日：2023-08-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

    IPC: H01L27/12

    CPC classification number: H01L27/1244

    Abstract: A film package includes: a film substrate having a first side surface and a second side surface opposing each other in a first direction, each of the first side surface and the second side surface extending in a second direction perpendicular to the first direction; at least one semiconductor chip disposed on the film substrate and extending lengthwise in the first direction; input terminals arranged on the film substrate along the first side surface, output terminals arranged on the film substrate along the second side surface, and wirings formed on the film substrate and electrically connecting the input terminals and the output terminals to the at least one semiconductor chip; and a protective layer covering the wirings on the film substrate.

    CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME
    13.
    发明公开
    CHIP ON FILM PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240096909A1

    公开(公告)日：2024-03-21

    申请号：US18200609

    申请日：2023-05-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Jaemin Jung ,  Jeongkyu Ha

    IPC: H01L27/12 ,  H05K7/20

    CPC classification number: H01L27/1244 ,  H05K7/20954

    Abstract: A chip on film (COF) package includes a film substrate including a base film having a mounting region, a main line pattern extending on the base film, and a branch line pattern extending on the base film and electrically connected to the main line pattern, a semiconductor chip vertically overlapping the mounting region, a first bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the main line pattern, and a second bump structure disposed between the semiconductor chip and the film substrate and electrically connected to the branch line pattern, the branch line pattern extends so as not to overlap a first edge of the first bump structure facing a first edge of the mounting region and a first edge of the second bump structure facing the first edge of the mounting region.

    Semiconductor memory device and method of adjusting operation condition of the same
    15.
    发明授权
    Semiconductor memory device and method of adjusting operation condition of the same 有权

    公开(公告)号：US12299296B2

    公开(公告)日：2025-05-13

    申请号：US18045590

    申请日：2022-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

    IPC: G11C11/401 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4097

    Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

    MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT
    16.
    发明公开
    MEMORY DEVICE INCLUDING FLEXIBLE COLUMN REPAIR CIRCUIT 审中-公开

    公开(公告)号：US20240006013A1

    公开(公告)日：2024-01-04

    申请号：US18296640

    申请日：2023-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyungjin Kim ,  Seunghyun Cho

    IPC: G11C29/44 ,  G06F11/10

    CPC classification number: G11C29/4401 ,  G06F11/1044

    Abstract: A memory device includes a memory cell array having a plurality of memory cells therein that span a plurality of rows, which are grouped into segments, and a plurality of columns, which are grouped into ticks. The ticks include normal ticks, and a spare tick that spans at least one redundancy column of memory cells in the memory cell array. A repair circuit is provided, which is configured to: (i) repair a first source address of a first failed column, which spans a plurality of the segments, with a first destination address of a pass column in one of the normal ticks, and then (ii) further repair the first destination address of the pass column with a first redundancy column within the spare tick that corresponds to the first destination address.

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    17.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20230289072A1

    公开(公告)日：2023-09-14

    申请号：US18045590

    申请日：2022-10-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seunghyun Cho ,  Youngju Kim ,  Younghwa Kim ,  Yujung Song ,  Reum Oh

    IPC: G06F3/06

    CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629 ,  G06F3/064

    Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME
    18.
    发明申请
    WORD LINE DRIVER CIRCUITS FOR MEMORY DEVICES AND METHODS OF OPERATING SAME 有权

    公开(公告)号：US20210225425A1

    公开(公告)日：2021-07-22

    申请号：US17038488

    申请日：2020-09-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sunggeun Do ,  Youngsik Kim ,  Gongheum Han ,  Sangyun Kim ,  Seunghyun Cho

    IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/406 ,  G11C5/06

    Abstract: A memory device includes a word line driver circuit, which can advantageously reduce gate stress on a transistor using a lower high voltage that varies with a command, and an operating method of the memory device. The memory device includes a plurality of memory blocks, provides a high voltage or the lower high voltage to a variable high voltage line in response to a block select signal, and changes a level of the lower high voltage to a low voltage level, a medium voltage level, or a high voltage level based on the command. The memory device applies the lower high voltage to gates of P-type metal oxide semiconductor (PMOS) transistors connected to a word line driving signal, which drives word lines of non-selected memory blocks among the plurality of memory blocks.

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