公开(公告)号：US20180166142A1

公开(公告)日：2018-06-14

申请号：US15889536

申请日：2018-02-06

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G11C16/34 ,  G11C11/56 ,  G11C29/52 ,  G11C29/44 ,  G06F11/10 ,  G11C16/10 ,  G11C29/04

CPC classification number: G11C16/3459 ,  G06F11/1048 ,  G11C11/56 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/34 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C2029/0411

Abstract: An apparatus comprises a memory and a controller. The memory configured to store data. The memory may comprise a write buffer and a plurality of memory dies. Each memory die may have a size less than a total size of the memory and include a plurality of cells. The memory may perform a program operation to write to and verify one or more of the plurality of cells in response to receiving a program command. The controller may be configured to issue the program command to program the plurality of memory dies and to issue the polling status command after issuing the program command to obtain a number of the cells that failed to be verified during the program operation. In response to the polling status command received from the controller, the memory reports a count of a number of bit-lines not having an inhibited state in the write buffer.

公开(公告)号：US09785499B2

公开(公告)日：2017-10-10

申请号：US14192110

申请日：2014-02-27

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F3/0616 ,  G06F11/1016

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to (i) classify data from multiple blocks of the memory as hot-read data or non hot-read data, (ii) aggregate the hot-read data to dedicated blocks, and (iii) select a type of error correcting code to protect the hot-read data in the dedicated blocks. The aggregation reduces an impact on endurance of the memory.

公开(公告)号：US09477423B2

公开(公告)日：2016-10-25

申请号：US14094900

申请日：2013-12-03

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Zhengang Chen ,  Erich Haratsch

IPC: G06F3/06 ,  G11C11/56

CPC classification number: G06F3/065 ,  G11C11/5628

Abstract: Mis-programming of MSB data in flash memory is avoided by maintaining a copy of LSB page data that has been written to flash memory and using the copy rather than the LSB page data read out of the flash cells in conjunction with the MSB values to determine the proper reference voltage ranges to be programmed into the corresponding flash cells. Because the copy is free of errors, using the copy in conjunction with the MSB values to determine the proper reference voltage ranges for the flash cells ensures that mis-programming of the reference voltage ranges will not occur.

Abstract translation: 通过将已写入闪速存储器的LSB页数据的副本与使用从闪存单元读出的LSB页数据结合MSB值来复制而不是使用复制而避免MSB数据的错误编程，以确定 正确的参考电压范围被编程到相应的闪存单元中。 由于复印件没有错误，因此使用复印件与MSB值一起确定闪存单元的正确参考电压范围，确保不会发生参考电压范围的错误编程。

公开(公告)号：US09218885B2

公开(公告)日：2015-12-22

申请号：US14191263

申请日：2014-02-26

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G11C16/28 ,  G11C16/10 ,  G11C11/56

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: An apparatus comprising a memory and a controller. The memory is configured to process a plurality of read/write operations. The memory comprises a plurality of memory modules. Each memory module has a size less than a total size of the memory. The controller is configured to write user data using a plurality of threshold voltages. The data considered hot-read data is written using a first voltage threshold. The data not considered hot-read data is written using a second voltage threshold. The first voltage threshold reduces an impact on endurance of the memory.

Abstract translation: 一种包括存储器和控制器的装置。 存储器被配置为处理多个读/写操作。 存储器包括多个存储器模块。 每个存储器模块的尺寸小于存储器的总大小。 控制器被配置为使用多个阈值电压写入用户数据。 使用第一电压阈值写入考虑热读数据的数据。 使用第二电压阈值写入不被认为是热读数据的数据。 第一个电压阈值降低了对存储器耐久性的影响。

公开(公告)号：US09213599B2

公开(公告)日：2015-12-15

申请号：US14041110

申请日：2013-09-30

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Zhengang Chen ,  Yu Cai ,  Erich F. Haratsch

IPC: G06F11/00 ,  H03M13/00 ,  G11C11/34 ,  G06F11/10 ,  G06F13/16 ,  G11C16/00 ,  G06F3/06 ,  G11C11/56 ,  G11C16/14 ,  G11C16/34

CPC classification number: G06F11/1068 ,  G06F3/06 ,  G06F13/16 ,  G11C11/5635 ,  G11C16/00 ,  G11C16/14 ,  G11C16/349

Abstract: An apparatus includes a non-volatile memory and a controller. The controller may be configured to track one or more channel parameters of the non-volatile memory. The controller may be further configured to estimate an erase state voltage distribution of the non-volatile memory by selecting one or more parameters of the erase state distribution from a look-up table based upon at least one of the one or more channel parameters.

Abstract translation: 一种装置包括非易失性存储器和控制器。 控制器可以被配置为跟踪非易失性存储器的一个或多个信道参数。 控制器还可以被配置为基于一个或多个信道参数中的至少一个从查找表中选择一个或多个擦除状态分布的参数来估计非易失性存储器的擦除状态电压分布。

公开(公告)号：US20150242268A1

公开(公告)日：2015-08-27

申请号：US14198862

申请日：2014-03-06

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Yu Cai ,  Zhengang Chen ,  Erich Haratsch

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/1072 ,  G06F2212/403 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Log likelihood ration (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

Abstract translation: 读取重试期间在闪存控制器中计算的对数似然比（LLR）值随着闪存存储器裸片的编程和擦除周期（PEC）的数量增加而随时间而变化。 因此，在使用LLR表向控制器的纠错码（ECC）解码逻辑提供预定义的固定LLR值的情况下，解码成功和所产生的BER将随时间而劣化，因为PEC的数目为 模具经受的增加。 根据实施例，提供存储系统，用于存储系统的闪存控制器和方法，其周期性地测量LLR值并用新的LLR值更新LLR表。 定期测量LLR值并用新的LLR值更新LLR表可以确保在闪存芯片寿命期间的高解码成功率和低BER。

公开(公告)号：US10580514B2

公开(公告)日：2020-03-03

申请号：US15884133

申请日：2018-01-30

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Yu Cai ,  Zhengang Chen ,  Erich Haratsch

IPC: G11C29/52 ,  G06F11/10 ,  G11C11/56 ,  G11C16/34 ,  G11C29/02 ,  G11C7/14 ,  G11C29/50 ,  G11C29/04

Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.

公开(公告)号：US10437513B2

公开(公告)日：2019-10-08

申请号：US15659267

申请日：2017-07-25

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Ning Chen ,  Erich F. Haratsch ,  Zhengang Chen

IPC: G06F3/06 ,  H03M13/11 ,  H03M13/00 ,  G06F12/02 ,  G06F11/10 ,  G11C16/08 ,  G11C29/52 ,  H03M13/37

Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

公开(公告)号：US10157096B2

公开(公告)日：2018-12-18

申请号：US15700727

申请日：2017-09-11

Applicant: Seagate Technology LLC

Inventor： Yu Cai ,  Yunxiang Wu ,  Erich F. Haratsch

IPC: G06F11/10 ,  G06F3/06

Abstract: An apparatus comprises a memory and a controller. The memory generally comprises a plurality of memory modules. The controller may be configured to process a plurality of read/write operations, classify data pages from multiple blocks of the memory as hot-read data or non hot-read data, and aggregate the hot-read data by selecting one or more of the hot-read data pages from multiple memory blocks and mapping the selected hot-read data pages to dedicated hot-read data blocks using a strong type of error correcting code during one or more of a garbage collection state, a data recycling state, or an idle state. The aggregation of the hot-read data pages and use of the strong type of error correcting code reduces read latency of the hot-read data pages, reduces a frequency of data recycling of the hot-read data pages, and reduces an impact of read disturbs on endurance of the memory.

公开(公告)号：US20180158536A1

公开(公告)日：2018-06-07

申请号：US15884133

申请日：2018-01-30

Applicant: Seagate Technology LLC

Inventor： Yunxiang Wu ,  Yu Cai ,  Zhengang Chen ,  Erich Haratsch

IPC: G11C29/52 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G11C29/02 ,  G11C7/14 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C29/52 ,  G06F11/1012 ,  G06F11/1072 ,  G06F2212/403 ,  G11C7/14 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Log likelihood ratio (LLR) values that are computed in a flash memory controller during read retries change over time as the number of program-and-erase cycles (PECs) that the flash memory die has been subjected to increases. Therefore, in cases where an LLR table is used to provide pre-defined, fixed LLR values to the error-correcting code (ECC) decoding logic of the controller, decoding success and the resulting BER will degrade over time as the number of PECs to which the die has been subjected increases. In accordance with embodiments, a storage system, a flash memory controller for use in the storage system and method are provided that periodically measure the LLR values and update the LLR table with new LLR values. Periodically measuring the LLR values and updating the LLR table with new LLR values ensures high decoding success and a low BER over the life of the flash memory die.