公开(公告)号：US20130222955A1

公开(公告)日：2013-08-29

申请号：US13835435

申请日：2013-03-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Kawae

IPC: H02H9/04

CPC classification number: H01L27/0255 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/861 ,  H02H9/044 ,  Y10S257/91

Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function φms of a source electrode in contact with the oxide semiconductor, the work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity λ of the oxide semiconductor satisfy φms≦λ

Abstract translation: 提供了使用氧化物半导体的非线性元件，例如二极管，并且整流性能良好。 在其中氢浓度小于或等于5×1019 / cm3的氧化物半导体的薄膜晶体管中，与氧化物半导体接触的源电极的功函数phim，漏电极的功函数phim 与氧化物半导体接触，并且氧化物半导体的电子亲和力λ满足λ

公开(公告)号：US20130140560A1

公开(公告)日：2013-06-06

申请号：US13753582

申请日：2013-01-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/786

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 在氧化物半导体层中形成的沟道的长度为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包含20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US20200243654A1

公开(公告)日：2020-07-30

申请号：US16846569

申请日：2020-04-13

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/417 ,  H01L29/786 ,  H01L27/12 ,  H01L51/10 ,  H01L29/49 ,  H01L51/05

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US09570628B2

公开(公告)日：2017-02-14

申请号：US14934387

申请日：2015-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/04 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，将氧化物半导体层和栅极绝缘层的厚度设定为15nm〜30nm，包括20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US08945962B2

公开(公告)日：2015-02-03

申请号：US13845443

申请日：2013-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yoshiyuki Kurokawa ,  Yasuhiro Jinbo ,  Satoshi Kobayashi ,  Daisuke Kawae

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/04 ,  H01L29/786 ,  H01L49/02 ,  H01L29/417 ,  H01L29/49

CPC classification number: H01L29/66765 ,  H01L28/40 ,  H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/78696

Abstract: In a method for manufacturing a semiconductor device including a transistor and a conductive film over a substrate, a first insulating film and a second insulating film are formed over the transistor and the conductive film sequentially. Then, an opening and a recessed portion are formed in the second insulating film using one multi-tone photomask, wherein the opening is deeper than the recessed portion in the second insulating film. By using the opening, a first contact hole exposing one of the electrodes of the transistor is formed through the first and second insulating films and, by using the recessed portion, a second contact hole exposing the first insulating film is formed through the second insulating film. Moreover, an electrode is formed on and in contact with the one of the electrodes in the first contact hole and the first insulating film in the second contact hole.

Abstract translation: 在衬底上制造包括晶体管和导电膜的半导体器件的方法中，依次在晶体管和导电膜上形成第一绝缘膜和第二绝缘膜。 然后，使用一个多色光掩模在第二绝缘膜中形成开口和凹部，其中开口比第二绝缘膜中的凹部更深。 通过使用开口，通过第一和第二绝缘膜形成暴露晶体管的一个电极的第一接触孔，并且通过使用凹部，暴露第一绝缘膜的第二接触孔通过第二绝缘膜形成 。 此外，在第一接触孔中的一个电极和第二接触孔中的第一绝缘膜上形成电极并与其接触。

公开(公告)号：US08680521B2

公开(公告)日：2014-03-25

申请号：US13753582

申请日：2013-01-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hiromichi Godo ,  Daisuke Kawae

IPC: H01L29/12

CPC classification number: H01L29/78693 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.

Abstract translation: 对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤， 其中形成沟道区。 将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，将氧化物半导体层和栅极绝缘层的厚度设定为15nm〜30nm，包括20nm〜50nm， 或分别为15nm〜100nm，10nm〜20nm。 因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

公开(公告)号：US20220149164A1

公开(公告)日：2022-05-12

申请号：US17582038

申请日：2022-01-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/417 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L51/05 ,  H01L51/10

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US09847396B2

公开(公告)日：2017-12-19

申请号：US15074287

申请日：2016-03-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kengo Akimoto ,  Daisuke Kawae

IPC: H01L29/786 ,  H01L27/32 ,  H01L29/417 ,  H01L51/05 ,  H01L29/49 ,  H01L51/10 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/41733 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/1288 ,  H01L29/4908 ,  H01L29/786 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0508 ,  H01L51/0512 ,  H01L51/0545 ,  H01L51/105

Abstract: A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

公开(公告)号：US09431427B2

公开(公告)日：2016-08-30

申请号：US14527204

申请日：2014-10-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiaki Oikawa ,  Hotaka Maruyama ,  Hiromichi Godo ,  Daisuke Kawae ,  Shunpei Yamazaki

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/24 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.

Abstract translation: 本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。 包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。 为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏极之间形成源极区或漏极区 层和包含SiOX的In-Sn-O系氧化物半导体层。 使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

公开(公告)号：US09385114B2

公开(公告)日：2016-07-05

申请号：US14337297

申请日：2014-07-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Daisuke Kawae

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/786 ,  H01L29/861 ,  H02H9/04

CPC classification number: H01L27/0255 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78642 ,  H01L29/7869 ,  H01L29/861 ,  H02H9/044 ,  Y10S257/91

Abstract: A non-linear element, such as a diode, in which an oxide semiconductor is used and a rectification property is favorable is provided. In a thin film transistor including an oxide semiconductor in which the hydrogen concentration is less than or equal to 5×1019/cm3, the work function φms of a source electrode in contact with the oxide semiconductor, the work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ

Abstract translation: 提供了使用氧化物半导体的非线性元件，例如二极管，并且整流性能良好。 在包含氢浓度小于或等于5×1019 / cm3的氧化物半导体的薄膜晶体管中，与氧化物半导体接触的源电极的功函数＆amp; ms， 与氧化物半导体接触的漏极，氧化物半导体的电子亲和力χ满足＆lt; ms＆nlE;χ＆phgr; md。 通过电连接薄膜晶体管的栅电极和漏电极，可以实现具有更好的整流特性的非线性元件。