公开(公告)号：US10109580B2

公开(公告)日：2018-10-23

申请号：US15367264

申请日：2016-12-02

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shunichiro Matsumoto ,  Hitoshi Kondo ,  Katsuya Fukase

IPC: H01L21/56 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A wiring board includes a single-layer insulating layer, and a single-layer interconnect layer embedded in the insulating layer, wherein an entirety of a first surface of the interconnect layer is exposed in a recessed position relative to a first surface of the insulating layer, and a second surface of the interconnect layer is partially exposed in a recessed position relative to a second surface of the insulating layer.

公开(公告)号：US10080292B2

公开(公告)日：2018-09-18

申请号：US15635590

申请日：2017-06-28

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Junji Sato ,  Hitoshi Kondo ,  Katsuya Fukase

IPC: H01L23/31 ,  H05K1/18 ,  H01L21/48 ,  H05K3/46 ,  H01L21/683 ,  H01L23/538 ,  H01L25/065 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H01L23/00

CPC classification number: H05K1/186 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19102 ,  H01L2924/386 ,  H05K1/111 ,  H05K1/115 ,  H05K3/4007 ,  H05K3/424 ,  H05K3/4682 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00012

Abstract: A wiring board includes an electronic component; an insulating layer containing the electronic component therein, and including a via hole that is open at one surface of the insulating layer to expose an electrode of the electronic component; a first wiring layer embedded in the insulating layer, one surface of the first wiring layer being exposed at the one surface of the insulating layer; a second wiring layer including a wiring pattern formed on the one surface of the first wiring layer, and a via wiring extended from the wiring pattern to be extended in the via hole and directly connected to an electrode of the electronic component.