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公开(公告)号：US20210280530A1
公开(公告)日：2021-09-09
申请号：US16876460
申请日：2020-05-18
Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
Inventor： Chi-Jen Chen , Chih-Hsun Hsu , Chee-Key Chung , Jia-Wei Pan , Chang-Fu Lin
IPC: H01L23/00 , H01L23/367 , H01L23/31 , H01L23/498
Abstract: Provided is an electronic package, including a multi-chip packaging body with a plurality of electronic elements and a stress buffer layer disposed on the multi-chip packaging body. The stress buffer layer is in contact with the plurality of electronic elements so as to cause stresses to be evenly distributed in the stress buffer layer instead of being concentrated in specific areas, thereby preventing structural stresses from being concentrated in corners of the electronic elements.
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公开(公告)号：US11102890B2
公开(公告)日：2021-08-24
申请号：US16201239
申请日：2018-11-27
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Ying-Chang Tseng , Yuan-Hung Hsu , Chang-Fu Lin
Abstract: This present disclosure provides an electronic package and a method for manufacturing the same. An antenna board with a limiter is stacked on a circuit board. A support body for holding the antenna board and the circuit board in place is provided between the antenna board and the circuit board, such that in the process of forming the support body, the limiter stops the flow of an adhesive material of the support body, and the adhesive material of the support body is prevented from overflowing onto an antenna structure of the antenna board to make sure that the antenna of the antenna board functions properly.
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公开(公告)号：US20210068260A1
公开(公告)日：2021-03-04
申请号：US17086888
申请日：2020-11-02
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Lung Huang , Chee-Key Chung , Chang-Fu Lin , Yuan-Hung Hsu
Abstract: A carrier structure is provided. A spacer is formed in an insulation board body provided with a circuit layer, and is not electrically connected to the circuit layer. The spacer breaks the insulation board body, and a structural stress of the insulation board body will not be continuously concentrated on a hard material of the insulation board body, thereby preventing warpage from occurring to the insulation board body.
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公开(公告)号：US10756438B2
公开(公告)日：2020-08-25
申请号：US15993243
申请日：2018-05-30
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Han-Hung Chen , Chun-Yi Huang , Chang-Fu Lin , Rung-Jeng Lin , Kuo-Hua Yu
Abstract: An electronic package and a method for fabricating the same are provided. A resist layer and a support are formed on a first substrate having a first antenna installation area. A second substrate having a second antenna installation area is laminated on the resist layer and the support. The resist layer is then removed. The support keeps the first substrate apart from the second substrate at a distance to ensure that the antenna transmission between the first antenna installation area and the second antenna installation area can function normally.
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公开(公告)号：US20190252344A1
公开(公告)日：2019-08-15
申请号：US15980255
申请日：2018-05-15
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Yu-Min Lo , Chee-Key Chung , Chang-Fu Lin , Kuo-Hua Yu , Hsiang-Hua Huang
Abstract: The present disclosure provides a method for manufacturing an electronic package, with an electronic component bonded to a carrier structure by means of solder tips formed on conductive bumps, wherein the solder tips do not require a reflow process to be in contact with the carrier structure, thereby allowing the conductive bumps to have an adequate amount of solder tips formed thereon and thus precluding problems such as cracking and collapsing of the solder tips.
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Patent Agency Ranking
公开(公告)号：US10354891B2
公开(公告)日：2019-07-16
申请号：US15945308
申请日：2018-04-04
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Po-Hao Wang , Chih-Jen Yang , Yu-Chih Cheng , Chee-Key Chung , Chang-Fu Lin
IPC: H01L23/52 , H01L21/56 , H01L23/31 , H01L23/498 , H01L23/00
Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
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公开(公告)号：US20190181021A1
公开(公告)日：2019-06-13
申请号：US15945308
申请日：2018-04-04
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Po-Hao Wang , Chih-Jen Yang , Yu-Chih Cheng , Chee-Key Chung , Chang-Fu Lin
IPC: H01L21/56 , H01L23/31 , H01L23/00 , H01L23/498
CPC classification number: H01L21/568 , H01L23/3128 , H01L23/49838 , H01L24/06 , H01L2224/04105 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/3512
Abstract: An electronic package and a method for fabricating the same are provided. The method includes forming a filling material, such as an underfill, between a carrier and a plurality of electronic components and filling the filling material in a space between the electronic components to form a spacing portion. The spacing portion has a first segment and a second segment separated from each other to serve as a stress buffer zone. Therefore, when an encapsulation layer encapsulating the electronic components is subsequently ground, the present disclosure can effectively prevent the electronic components from being cracked due to stresses induced by the external grinding force.
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公开(公告)号：US20190164861A1
公开(公告)日：2019-05-30
申请号：US16170904
申请日：2018-10-25
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Wen-Shan Tsai , Chee-Key Chung , Chang-Fu Lin
Abstract: An electronic package and a method for fabricating the same are provided. The method includes disposing on a carrier an electronic component having a plurality of conductors, encapsulating the electronic component with an encapsulant, and disposing an electronic device on the encapsulant. The electronic device and the carrier are electrically connected through the conductors, thereby reducing the overall thickness of the electronic package.
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公开(公告)号：US20180269142A1
公开(公告)日：2018-09-20
申请号：US15590111
申请日：2017-05-09
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chee-Key Chung , Yu-Min Lo , Han-Hung Chen , Chang-Fu Lin , Fu-Tang Huang
IPC: H01L23/498 , H01L23/14 , H01L23/28
CPC classification number: H01L23/49827 , H01L23/147 , H01L23/28 , H01L23/3128 , H01L23/3135 , H01L23/49816 , H01L2224/32225 , H01L2224/73204 , H01L2924/181 , H01L2924/18161 , H01L2924/00012
Abstract: The disclosure provides a substrate construction applicable to a 3D package, including a silicon substrate for carrying a chip on an upper side thereof, and a circuit structure formed underneath the silicon substrate for being connected to solder balls via conductive pads of the circuit structure, thereby obtaining the same specification of the conductive pads as ball-planting pads of conventional package substrates and avoiding the manufacturing and use of conventional package substrates.
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20.发明申请公开(公告)号：US20160099204A1
公开(公告)日：2016-04-07
申请号：US14709510
申请日：2015-05-12
Applicant: Siliconware Precision Industries Co., Ltd.
Inventor： Chang-Fu Lin , Chin-Tsai Yao , Chia-Cheng Chen , Chih-Jen Yang , Fu-Tang Huang
CPC classification number: H01L23/49838 , H01L23/3121 , H01L23/49811 , H01L23/49822 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/131 , H01L2224/14131 , H01L2224/14133 , H01L2224/16227 , H01L2224/16238 , H01L2224/17106 , H01L2224/81193 , H01L2224/81385 , H01L2224/81801 , H01L2924/18161 , H01L2924/381 , H01L2924/3841 , H05K1/111 , H05K2201/0367 , H05K2201/0376 , H05K2201/09227 , H05K2201/10674 , Y02P70/611 , H01L2924/014 , H01L2924/00014
Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.
Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。
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