公开(公告)号：US10679932B2

公开(公告)日：2020-06-09

申请号：US15499446

申请日：2017-04-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367

Abstract: A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.

公开(公告)号：US20180061810A1

公开(公告)日：2018-03-01

申请号：US15372638

申请日：2016-12-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Kuo-Hua Yu ,  Fu-Tang Huang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13541 ,  H01L2224/16013 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17132 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3512 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09607963B2

公开(公告)日：2017-03-28

申请号：US14258361

申请日：2014-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/17106 ,  H01L2224/73204 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00012

Abstract: A semiconductor device is disclosed, which includes: a substrate having a substrate body and a plurality of conductive pads formed on the substrate body, wherein each of the conductive pads has at least an opening formed in a first surface thereof; a semiconductor component having a plurality of bonding pads; a plurality of conductive elements formed between the bonding pads and the conductive pads and in the openings of the conductive pads; and an encapsulant formed between the substrate and the semiconductor component for encapsulating the conductive elements, thereby strengthening the bonding between the conductive elements and the conductive pads and consequently increasing the product yield.

公开(公告)号：US09190387B2

公开(公告)日：2015-11-17

申请号：US14253324

申请日：2014-04-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L23/495 ,  H01L23/552 ,  H01L23/31

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

Abstract translation: 提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕 裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。 进一步提出如上所述的制造封装结构的方法。

公开(公告)号：US20150069605A1

公开(公告)日：2015-03-12

申请号：US14272764

申请日：2014-05-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Hung-Ming Chang ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/498

CPC classification number: H01L21/76895 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/014

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

Abstract translation: 公开了一种半导体器件，其包括：具有多个连接焊盘的衬底; 半导体部件，其具有形成在其表面上并对应于所述连接焊盘的多个焊盘和形成在所述焊盘上的UBM层; 多个导电元件，其各自具有依次形成在所述UBM层上的第一导电部分和第二导电部分，其中所述第二导电部分的宽度小于所述第一导电部分; 以及形成在第二导电部分和连接焊盘之间的多个焊球，用于连接半导体部件和衬底，从而防止在相邻的导电元件之间发生焊料桥接并减小导电元件与UBM层之间的应力。

公开(公告)号：US20160099204A1

公开(公告)日：2016-04-07

申请号：US14709510

申请日：2015-05-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chia-Cheng Chen ,  Chih-Jen Yang ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17106 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.

Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。

公开(公告)号：US20150237717A1

公开(公告)日：2015-08-20

申请号：US14453977

申请日：2014-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-fu Lin Chang ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H05K1/02 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0191 ,  H05K2201/09736 ,  H05K2201/20 ,  H05K2203/0353 ,  H05K2203/0369 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

Abstract translation: 提供一种封装基板，其包括多个电介质层和与电介质层交替堆叠的多个电路层。 至少两个电路层的厚度不同，以防止基板翘曲。

公开(公告)号：US20150155240A1

公开(公告)日：2015-06-04

申请号：US14622255

申请日：2015-02-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L21/56 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/78 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An EMI shielding package structure includes a substrate unit having a first surface with a die mounting area and a second surfaces opposite to the first surface, metallic pillars formed on the first surface, a chip mounted on and electrically connected to the die-mounting area, an encapsulant covering the chip and the first surface while exposing a portion of each of the metallic pillars from the encapsulant, and a shielding film enclosing the encapsulant and electrically connecting to the metallic pillars. A fabrication method of the above structure by two cutting processes is further provided. The first cutting process forms grooves by cutting the encapsulant. After a shielding film is formed in the grooves and electrically connected to the metallic pillars, the complete package structure is formed by the second cutting process, thereby simplifying the fabrication process while overcoming inferior grounding of the shielding film as encountered in prior techniques.

Abstract translation: EMI屏蔽封装结构包括具有第一表面和芯片安装区域的基板单元和与第一表面相对的第二表面，形成在第一表面上的金属柱，安装在芯片安装区域上并与之电连接的芯片， 在将所述金属柱的一部分从所述密封剂暴露出来的同时覆盖所述芯片和所述第一表面的密封剂以及封装所述密封剂并电连接到所述金属柱的屏蔽膜。 进一步提供通过两个切割工艺的上述结构的制造方法。 第一切割工艺通过切割密封剂形成凹槽。 在凹槽中形成屏蔽膜并与金属柱电连接之后，通过第二切割工艺形成完整的封装结构，从而在克服现有技术中遇到的屏蔽膜的不良接地的同时简化制造工艺。

公开(公告)号：US09013042B2

公开(公告)日：2015-04-21

申请号：US13677861

申请日：2012-11-15

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao ,  Jui-Chung Ho ,  Ching-Hui Hung

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53204 ,  H01L24/00 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05584 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/16503 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps.

Abstract translation: 提供了用于形成在半导体封装中的衬底的焊盘上的互连结构。 互连结构包括形成在每个接合焊盘上的镍层，形成在镍层上的金属层和形成在金属层上的焊料材料。 金属层由金，银，铅和铜之一制成，厚度为0.5〜5μm。 因此，当焊料材料回流以形成焊料凸块时，在焊料凸块和金属层之间不形成镍锡化合物，从而避免焊料凸块的开裂或分层。

公开(公告)号：US20180130774A1

公开(公告)日：2018-05-10

申请号：US15434824

申请日：2017-02-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Kuo-Hua Yu ,  Fu-Tang Huang

IPC: H01L25/065 ,  H01L23/31

Abstract: A package stack structure is provided, including a first substrate, a second substrate stacked on the first substrate, and an encapsulant formed between the first substrate and the second substrate. A through hole is formed to penetrate the second substrate and allow the encapsulant to be filled therein, thereby increasing the contact area and hence strengthening the bonding between the encapsulant and the second substrate.