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11.发明授权公开(公告)号：US10373679B1
公开(公告)日：2019-08-06
申请号：US15604562
申请日：2017-05-24
Applicant: SK hynix Inc.
Inventor： Woo-Tae Lee , Seok-Man Hong , Myoung-Sub Kim , Tae-Hoon Kim , Hyun-Jeong Kim
Abstract: A method for reading data of a memory cell including a resistive memory element having a low resistance state and a high resistance state according to stored data and a selection element may include applying a recovery voltage to both ends of the memory cell, and applying a read voltage to both ends of the memory cell and sensing the data. The recovery voltage may be equal to or more than a second voltage obtained by adding a drift value of the memory cell to a first voltage for turning on the memory cell in a case in which the resistive memory element is in the low resistance state.
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公开(公告)号：US10541011B1
公开(公告)日：2020-01-21
申请号：US16049644
申请日：2018-07-30
Applicant: SK hynix Inc.
Inventor： Seok-Man Hong , Tae-Hoon Kim
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell; a first line coupled to a first end of the memory cell; a first coupling circuit to selectively couple a high voltage terminal to the first line in response to a first selection signal; a second line coupled to a second end of the memory cell; a second coupling circuit to selectively couple a first low voltage terminal to the second line in response to a second selection signal; and a first charge storing circuit selectively coupled to the first line in response to an enable signal, the enable signal corresponding to a predetermined operation mode when the memory cell is turned on.
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13.发明授权公开(公告)号：US10115461B1
公开(公告)日：2018-10-30
申请号：US15605603
申请日：2017-05-25
Applicant: SK hynix Inc.
Inventor： Woo-Tae Lee , Seok-Man Hong , Tae-Hoon Kim , Sang-Hyun Ban , Hye-Jung Choi
Abstract: An electronic device includes a semiconductor memory, and the semiconductor memory includes a memory cell including a resistive memory element having a high resistance state and a low resistance state according to stored data, a selection element coupled serially to the resistive memory element, and a current clamping transistor electrically connected to a first end of the memory cell to limit an amount of a current flowing through the memory cell. In a drift recovery operation of the memory cell, a rising pulse voltage may be applied to a second end of the memory cell in a state in which the current clamping transistor has been turned off, the first end facing the second end.
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公开(公告)号：US10056138B1
公开(公告)日：2018-08-21
申请号：US15605661
申请日：2017-05-25
Applicant: SK hynix Inc.
Inventor： Hyun-Jeong Kim , Myoung-Sub Kim , Tae-Hoon Kim , Seung-Hwan Lee , Woo-Tae Lee
CPC classification number: G11C13/0026 , G11C8/10 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/2253 , G11C11/2255 , G11C11/2257 , G11C13/0023 , G11C13/0028
Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include a memory region comprising a plurality of memory cells disposed at respective intersections between a plurality of row lines and a plurality of column lines, the plurality of row lines extending in a first direction, the plurality of column lines extending in a second direction crossing the first direction; first and second row drivers arranged on one side and the other side of the memory region in the first direction, respectively, and driving a common row line corresponding to a row address among the plurality of row lines; and a column driver driving a common column line corresponding to a column address among the plurality of column lines, wherein the first and second row drivers are coupled to the common row line.
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15.发明申请公开(公告)号：US20180124337A1
公开(公告)日：2018-05-03
申请号：US15786379
申请日：2017-10-17
Applicant: SK hynix Inc.
Inventor： Tae-Hoon Kim
CPC classification number: H04N5/3575 , H04N5/225 , H04N5/3698 , H04N5/374 , H04N5/378
Abstract: An image sensor device is provided to include: a pixel bias voltage sampling unit suitable for sampling a pixel bias voltage; a pixel power noise addition control unit suitable for controlling the magnitude of added pixel power noise; a pixel power noise addition unit suitable for adding pixel power noise to a node of the pixel bias voltage sampled by the pixel bias voltage sampling unit according to control of the pixel power noise addition control unit; and a biasing unit suitable for offsetting pixel power noise transmitted from the pixel by inverting the pixel power noise added by the pixel power noise addition unit.
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Patent Agency Ranking
公开(公告)号：US09276500B2
公开(公告)日：2016-03-01
申请号：US14106792
申请日：2013-12-15
Applicant: SK hynix Inc.
Inventor： Boo-Ho Jung , Sung-Woo Han , Ic-Su Oh , Jun-Ho Lee , Hyun-Seok Kim , Sun-Ki Cho , Tae-Hoon Kim , Ki-Chul Hong
IPC: G11C11/401 , H02M11/00 , G11C5/06 , G11C5/14 , G11C7/02 , G11C11/4074
CPC classification number: H02M11/00 , G11C5/063 , G11C5/14 , G11C7/02 , G11C11/4074
Abstract: A reservoir capacitor includes a first capacitor group having two or more capacitors, which are serially coupled to each other between a first power voltage supply terminal and a second power voltage supply terminal, a second capacitor group having two or more capacitors, which are serially coupled to each other between a third power voltage supply terminal and a fourth power voltage supply terminal and a connection line suitable for electrically coupling a first coupling node between the capacitors of the first capacitor group to a second coupling node between the capacitors of the second capacitor group.
Abstract translation: 蓄电池电容器包括具有两个或更多个电容器的第一电容器组，其在第一电源电压端子和第二电源电压端子之间彼此串联耦合，第二电容器组具有两个或更多个电容器，其串联耦合 在第三电源电压端子与第四电源电压端子之间相互连接的第二电容器组和适于将第一电容器组的电容器之间的第一耦合节点电耦合到第二电容器组的电容器之间的第二耦合节点的连接线 。
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公开(公告)号：US11342043B2
公开(公告)日：2022-05-24
申请号：US16860566
申请日：2020-04-28
Applicant: SK hynix Inc.
Inventor： Sang-Hyun Ban , Tae-Hoon Kim , Woo-Tae Lee , Hye-Jung Choi
Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a plurality of first lines; a plurality of second lines; a plurality of memory cells disposed in respective intersection regions between the plurality of first lines and the plurality of second lines; a first test circuit configured to apply a stress pulse to a first selection line coupled to a defective memory cell among the plurality of memory cells during a first test period, in response to a first test control signal, the first selection line including any one of the plurality of first lines; and a control unit configured to generate the first test control signal based on a first test mode signal.
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公开(公告)号：US11170824B2
公开(公告)日：2021-11-09
申请号：US17088334
申请日：2020-11-03
Applicant: SK hynix Inc.
Inventor： Myoung-Sub Kim , Tae-Hoon Kim , Hye-Jung Choi , Seok-Man Hong
IPC: G11C5/02 , H01L27/22 , G11C13/00 , H01L27/108
Abstract: A semiconductor memory includes: a first line; a second line spaced apart from the first line and extending in a first direction; a third line spaced apart from the second line and extending in a second direction; a first memory cell disposed between the first and second lines at an intersection region of the first and second lines, the first memory cell including a first selection element layer, a first electrode, and a first insert electrode interposed between the first selection element layer and the first electrode; and a second memory cell disposed between the second and third lines at an intersection region of the second and third lines, the second memory cell including a second selection element layer, a second electrode, and a second insert electrode interposed between the second selection element layer and the second electrode.
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公开(公告)号：US11164654B2
公开(公告)日：2021-11-02
申请号：US16997652
申请日：2020-08-19
Applicant: SK hynix Inc.
Inventor： Sang-Hyun Ban , Tae-Hoon Kim , Woo-Tae Lee , Hye-Jung Choi
IPC: G11C29/50 , G11C11/16 , G11C13/00 , G06F12/0802 , G11C29/04 , H01L27/22 , H01L45/00 , H01L43/08 , H01L27/24 , H01L23/528 , H01L43/10 , H01F10/32
Abstract: A method drives an electronic device including a semiconductor memory in a test mode. The method includes applying a stress pulse simultaneously to a plurality of memory cells to turn on the plurality of memory cells, determining whether the memory cells are turned on or turned off, and applying a second maximum voltage to a selected memory cell of the plurality of memory cells only when the selected memory cell is determined to be in a turned-off state.
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公开(公告)号：US10896702B2
公开(公告)日：2021-01-19
申请号：US16547447
申请日：2019-08-21
Applicant: SK hynix Inc.
Inventor： Seok-Man Hong , Tae-Hoon Kim
IPC: G11C7/10 , G11C11/404 , H01L27/22 , G11C11/407 , G11C16/26 , G11C13/00 , G11C11/56 , G11C7/06 , G11C29/02
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.
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