公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US20240280613A1

公开(公告)日：2024-08-22

申请号：US18567039

申请日：2022-08-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Shen XU ,  Chenxi YANG ,  Yijie QIAN ,  Yujie LIU ,  Limin YU ,  Weifeng SUN ,  Longxing SHI

IPC: G01R19/25 ,  G01R15/04 ,  G01R19/00 ,  H02M1/00 ,  H02M3/157 ,  H02M3/158

CPC classification number: G01R19/25 ,  G01R15/04 ,  G01R19/0038 ,  H02M1/0009 ,  H02M3/157 ,  H02M3/158

Abstract: An inductor current estimation method for a DC-DC switching power supply using a voltage sampling module, a data conversion module, a switching signal counting module, an inductor voltage calculation module and a digital filter module, comprising: processing an input voltage and an output voltage by the voltage sampling module and the data conversion module to obtain a converted input voltage and a converted output voltage which have a same number of bits; comparing a node voltage with a reference voltage, and then obtaining a duty cycle by the switching signal counting module; and then, outputting an average voltage of two terminals of an inductor and a parasitic resistor by the inductor voltage calculation module, and finally, obtaining an estimated inductor current by the digital filter module.

公开(公告)号：US20230019004A1

公开(公告)日：2023-01-19

申请号：US17762206

申请日：2020-09-25

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jiaxing WEI ,  Qichao WANG ,  Kui XIAO ,  Dejin WANG ,  Li LU ,  Ling YANG ,  Ran YE ,  Siyang LIU ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/78

Abstract: A lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), including: a trench gate including a lower part inside a trench and an upper part outside the trench, a length of the lower part in a width direction of a conducting channel being less than that of the upper part, and the lower part extending into a body region and having a depth less than that of the body region; an insulation structure arranged between a drain region and the trench gate and extending downwards into a drift region, a depth of the insulation structure being less than that of the drift region.

公开(公告)号：US20220069115A1

公开(公告)日：2022-03-03

申请号：US17417663

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Siyang LIU ,  Chi ZHANG ,  Kui XIAO ,  Guipeng SUN ,  Dejin WANG ,  Jiaxing WEI ,  Li LU ,  Weifeng SUN ,  Shengli LU

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/207

Abstract: A heterojunction semiconductor device with a low on-resistance includes a metal drain electrode, a substrate, and a buffer layer. A current blocking layer arranged in the buffer layer, a gate structure is arranged on the buffer layer, and the gate structure comprises a metal gate electrode, GaN pillars and AlGaN layers, wherein a metal source electrode is arranged above the metal gate electrode; and the current blocking layer comprises multiple levels of current blocking layers, the centers of symmetry of the layers are collinear, and annular inner openings of the current blocking layers at all levels gradually become smaller from top to bottom. The AlGaN layers and the GaN pillars are distributed in a honeycomb above the buffer layer.

公开(公告)号：US20210336009A1

公开(公告)日：2021-10-28

申请号：US16486494

申请日：2018-09-25

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Lizhi TANG ,  Sheng LI ,  Chi ZHANG ,  Jiaxing WEI ,  Shengli LU ,  Longxing SHI

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78

Abstract: The invention provides a graphene channel silicon carbide power semiconductor transistor, and its cellular structure thereof. Characterized in that, a graphene strip serving as a channel is embedded in a surface of the P-type body region and two ends of the graphene strip are respectively contacted with a boundary between the N+-type source region and the P-type body region and a boundary between the P-type body region and the N-type drift region, and the graphene strip is distributed in a cellular manner in a gate width direction, a conducting channel of a device is still made of graphene; in the case of maintaining basically invariable on-resistance and current transmission capacity, the P-type body regions are separated by the graphene strip, thus enhancing a function of assisting depletion, which further reduces an overall off-state leakage current of the device, and improves a breakdown voltage.

公开(公告)号：US20220115532A1

公开(公告)日：2022-04-14

申请号：US17417677

申请日：2019-12-23

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng SUN ,  Rongcheng LOU ,  Kui XIAO ,  Feng LIN ,  Jiaxing WEI ,  Sheng LI ,  Siyang LIU ,  Shengli LU ,  Longxing SHI

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66

Abstract: A power semiconductor device includes a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

公开(公告)号：US20220085727A1

公开(公告)日：2022-03-17

申请号：US17418606

申请日：2019-12-19

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Weifeng SUN ,  Huaxin ZHANG ,  Hu ZHANG ,  Menglin YU ,  Siyu ZHAO ,  Shen XU ,  Longxing SHI

IPC: H02M3/335

Abstract: A flyback converter and an output voltage acquisition method therefor and apparatus thereof, wherein the output voltage acquisition method comprises the following steps: acquiring the reference output voltage of a flyback converter; sampling the current output voltage of the flyback converter within a reset time of each switching period among M continuous switching periods of the flyback converter, wherein M is a positive integer; and according to the reference output voltage and the current output voltage, sampling a dichotomy to successively approximate the current output voltage until the M switching periods are finished, and acquiring the output voltage of the flyback converter.

公开(公告)号：US20210234030A1

公开(公告)日：2021-07-29

申请号：US16969437

申请日：2019-10-21

Applicant: SOUTHEAST UNIVERSITY

Inventor： Weifeng SUN ,  Siyang LIU ,  Sheng LI ,  Chi ZHANG ,  Xinyi TAO ,  Ningbo LI ,  Longxing SHI

IPC: H01L29/778

Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

公开(公告)号：US20210218396A1

公开(公告)日：2021-07-15

申请号：US17044623

申请日：2020-04-15

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing ZHU ,  Weifeng SUN ,  Bowei YANG ,  Siyuan YU ,  Yangyang LU ,  Longxing SHI ,  Shengli LU

IPC: H03K17/687 ,  H03K19/20

Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

公开(公告)号：US20200343845A1

公开(公告)日：2020-10-29

申请号：US16958868

申请日：2018-12-29

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

Inventor： Rui ZHONG ,  Mingshu ZHANG ,  Sen ZHANG ,  Jinyu XIAO ,  Wei SU ,  Weifeng SUN ,  Longxing SHI

IPC: H02P25/08 ,  H02P23/04

Abstract: A method and an apparatus for reducing noise of a switched reluctance motor, includes: supplying a PWM signal as a driving signal to a driving circuit of a switched reluctance motor; and varying a carrier frequency of the PWM signal as an operation period of the switched reluctance motor varies; if the switched reluctance motor changes phase, determining that the operation period of the switched reluctance motor varies.